Cirrus-logic EP93xx Instrukcja Użytkownika Pobierz pdf (Strona 579)

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101

DS785UM1 16-3

UART3 With HDLC Encoder

EP93xx User’s Guide

As another example, assume 230,400 baud (the maximum with a UARTCLK equal to

7.3728 Mhz), 5-bit characters, no parity, one stop bit, and no space between characters.

There are 7 bits per character, so 230,400 / 7 = 32,914 characters per second. Simultaneous

transmitting and receiving implies 65,829 APB characters per second. Using the DMA

interface would result in 16,457 AHB accesses per second, while using the APB to access

the UART leads to 65,829 bus accesses per second.

16.3 Registers

UART3Data

Address:

0x808E_0000 - Read/Write

Default:

0x0000_0000

Definition:

UART3 Data Register

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

DATA: UART Data, read for receive data, write for transmit data

For words to be transmitted:

• if the FIFOs are enabled, data written to this location is

pushed onto the transmit FIFO

• if the FIFOs are not enabled, data is stored in the

transmitter holding register (the bottom word of the

transmit FIFO). The write operation initiates transmission

from the UART. The data is prefixed with a start bit,

appended with the appropriate parity bit (if parity is

enabled), and a stop bit. The resultant word is then

transmitted.

For received words:

• if the FIFOs are enabled, the data byte is extracted, and

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

1514131211109876543210

RSVD DATA

1 2 ... 574 575 576 577 578 579 580 581 582 583 584 ... 823 824

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