Cirrus-logic EP93xx Instrukcja Użytkownika Pobierz pdf (Strona 557)

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101

DS785UM1 14-35

UART1 With HDLC and Modem Control Signals

EP93xx User’s Guide

RFS: Receive FIFO Service request. (Read Only)

This bit is a copy of the RIS bit in the UART interrupt

identification register.

0 - RX FIFO is empty or RX is disabled.

1 - RX FIFO not empty and RX enabled.

May generate an interrupt and signal a DMA service

request.

TAB: Transmitted Frame Aborted. (Read/Write)

Set “1” when a transmitted frame is terminated with an

abort. Cleared by writing to a “1” to this bit.

TFC: Transmit Frame Complete. (Read/Write)

Set to “1” whenever a transmitted frame completes,

whether terminated normally or aborted. Cleared by

writing to a “1” to this bit.

TFS: Transmit FIFO Service request. (Read Only)

This bit is a copy of the TIS bit in the UART interrupt

identification register.

0 - TX FIFO is full or TX disabled.

1 - TX FIFO not full and TX enabled. May generate an

interrupt and signal a DMA service request.

1 2 ... 552 553 554 555 556 557 558 559 560 561 562 ... 823 824

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