Cirrus-logic EP93xx Instrukcja Użytkownika Pobierz pdf (Strona 156)

100

101

5-30 DS785UM1

System Controller

EP93xx User’s Guide

MIRClkDiv

Address:

0x8093_0088 - Read/Write, Software locked

Default:

0x0000_0000

Definition:

Configures MIR clock for the MIR IrDA. Selects input to MIR clock dividers

from either PLL1 or PLL2, and defines a programmable divide value.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

MENA: Enable MIR_CLK divider.

ESEL: External clock source select.

0 - Use the external XTALI clock input as the clock source.

1 - Use one of the internal PLLs selected by PSEL as the

clock source.

PSEL: PLL source select.

1 - Select PLL2 as the clock source.

0 - Select PLL1 as the clock source.

PDIV: Pre-divider value. Generates divide by 2, 2.5, or 3 from the

clock source.

00 - Disable clock

01 - Divide-by-2

10 - Divide-by-2.5

11 - Divide-by-3

MDIV: MIR_CLK divider value. Forms a divide-by-N of the pre-

divide clock output. MIR_CLK is the source clock divided

by PDIV divided by N.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

1514131211109876543210

MENA ESEL PSEL RSVD PDIV RSVD MDIV

1 2 ... 151 152 153 154 155 156 157 158 159 160 161 ... 823 824

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