Cirrus-logic EP93xx Instrukcja Użytkownika Pobierz pdf (Strona 545)

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DS785UM1 14-23

UART1 With HDLC and Modem Control Signals

EP93xx User’s Guide

Address:

0x808C_0018 - Read Only

Default:

0x0000_0000

Definition:

UART Flag Register

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

TXFE: Transmit FIFO Empty. The meaning of this bit depends on

the state of the FEN bit in the UART1LinCtrlHigh register.

If the FIFO is disabled, this bit is set when the transmit

holding register is empty. If the FIFO is enabled, the TXFE

bit is set when the transmit FIFO is empty.

RXFF: Receive FIFO Full. The meaning of this bit depends on the

state of the FEN bit in the UART1LinCtrlHigh register. If

the FIFO is disabled, this bit is set when the receive

holding register is full. If the FIFO is enabled, the RXFF bit

is set when the receive FIFO is full.

TXFF: Transmit FIFO Full. The meaning of this bit depends on

the state of the FEN bit in the UART1LinCtrlHigh register.

If the FIFO is disabled, this bit is set when the transmit

holding register is full. If the FIFO is enabled, the TXFF bit

is set when the transmit FIFO is full.

RXFE: Receive FIFO Empty. The meaning of this bit depends on

the state of the FEN bit in the UART1LinCtrlHigh register.

If the FIFO is disabled, this bit is set when the receive

holding register is empty. If the FIFO is enabled, the RXFE

bit is set when the receive FIFO is empty.

BUSY: UART Busy. If this bit is set to 1, the UART is busy

transmitting data. This bit remains set until the complete

byte, including all the stop bits, has been sent from the

shift register. This bit is set as soon as the transmit FIFO

becomes non-empty (regardless of whether the UART is

enabled or not).

DCD: Data Carrier Detect status. This bit is the complement of

the UART data carrier detect (nUARTDCD) modem status

input. That is, the bit is 1 when the modem status input is

DSR: Data Set Ready status. This bit is the complement of the

UART data set ready (nUARTDSR) modem status input.

That is, the bit is 1 when the modem status input is 0.

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