Cirrus-logic CS5376A Instrukcja Użytkownika Pobierz pdf (Strona 99)

CS5376A

DS612F4 99

23.2.13 SYSTEM1, SYSTEM2 : 0x2C, 0x2D

(MSB) 23 22 21 20 19 18 17 16

SYS23 SYS22 SYS21 SYS20 SYS19 SYS18 SYS17 SYS16

R/WR/WR/WR/WR/WR/WR/WR/W

00000000

15 14 13 12 11 10 9 8

SYS15 SYS14 SYS13 SYS12 SYS11 SYS10 SYS9 SYS8

R/WR/WR/WR/WR/WR/WR/WR/W

00000000

7654321(LSB) 0

SYS7 SYS6 SYS5 SYS4 SYS3 SYS2 SYS1 SYS0

R/WR/WR/WR/WR/WR/WR/WR/W

00000000

DF Address: 0x2C

-- Not defined;

read as 0

R Readable

W Writable

R/W Readable and

Writable

Bits in bottom rows

are reset condition

Figure 57. User Defined System Register SYSTEM1

Bit definitions:

23:16 SYS[23:16] System Register

Upper Byte

15:8 SYS[15:8] System Register

Middle Byte

15:8 SYS[7:0] System Register

Lower Byte

1 2 ... 94 95 96 97 98 99 100 101 102 103 104 105 106

Features 1
Description 1
TABLE OF CONTENTS 2
DS612F4 3 3
LIST OF FIGURES 4
DS612F4 5 5
LIST OF TABLES 6
1. GENERAL DESCRIPTION 7
1.1 Digital Filter Features 7
1.3 System Level Features 8
1.4 Configuration Interface 9
DS612F4 10 10
SPI 1 Registers 12
Digital Filter Registers 12
ABSOLUTE MAXIMUM RATINGS 13
THERMAL CHARACTERISTICS 14
DIGITAL CHARACTERISTICS 14
POWER CONSUMPTION 14
SWITCHING CHARACTERISTICS 15
3. SYSTEM DESIGN WITH CS5376A 19
3.1 Power Supplies 19
3.2 Reset Control 19
20 DS612F4 20
4. POWER SUPPLIES 21
4.1 Pin Descriptions 21
4.2 Bypass Capacitors 22
4.3 Power Consumption 22
5. RESET CONTROL 23
5.1 Pin Descriptions 23
5.2 Reset Self-Tests 23
5.3 Boot Configurations 23
6. CLOCK GENERATION 24
6.1 Pin Description 24
6.2 Synchronous Clocking 24
8. CONFIGURATION BY EEPROM 26
8.1 Pin Descriptions 26
8.2 EEPROM Hardware Interface 26
8.3 EEPROM Organization 26
SPI 1 Read from EEPROM 27
8.4 EEPROM Configuration 28
Commands 28
Sample Command: 28
DS612F4 31 31
9.1 Pin Descriptions 32
34 DS612F4 34
DS612F4 37 37
DS612F4 38 38
10.MODULATOR INTERFACE 39
10.1Pin Descriptions 39
10.3Modulator Synchronization 39
10.4Modulator Data Inputs 40
10.5Modulator Flag Inputs 40
Correction 41
42 DS612F4 42
12.SINC FILTER 43
12.1SINC1 Filter 43
12.2SINC2 Filter 43
12.3SINC3 Filter 43
SINC filters 44
DS612F4 46 46
13.FIR FILTER 47
13.1FIR1 Filter 47
13.2FIR2 Filter 47
13.3On-Chip FIR Coefficients 47
48 DS612F4 48
SINC + FIR filters 49
DS612F4 50 50
Minimum phase group delay 51
DS612F4 52 52
DS612F4 53 53
DS612F4 54 54
DS612F4 55 55
14.4IIR3 Filter 56
14.5On-Chip IIR Coefficients 56
IIR filters 57
58 DS612F4 58
DS612F4 59 59
60 DS612F4 60
DS612F4 61 61
FIFO Overflow Bit - W 62
Conversion Data Word 62
16.3.1 Request Mode 62
16.3.2 Continuous Mode 63
64 DS612F4 64
66 DS612F4 66
TIMEB - Pin 57 67
68 DS612F4 68
DS612F4 69 69
CS[4:0] - Pins 32 - 36 70
SCK2 - Pin 31 70
SO - Pin 30 70
SI[4:1] - Pins 26 - 29 70
DS612F4 71 71
20.3.3 SPI 2 Data Register 72
Write Transactions 72
Read Transactions 72
SPI Modes 72
SPI 2 Write to External Slave 73
DS612F4 74 74
TRST - Pin 1 75
TMS - Pin 2 75
TCK - Pin 3 75
TDI - Pin 4 75
TDO - Pin 5 75
21.2.1 JTAG Reset 76
21.2.2 TAP Controller 76
21.2.3 Boundary Scan Cells 76
DS612F4 77 77
DS612F4 78 78
DS612F4 79 79
80 DS612F4 80
23.REGISTER SUMMARY 81
23.1SPI 1 Registers 81
82 DS612F4 82
SPI 1 Address: 0x00 82
DS612F4 83 83
SPI 1 Address: 0x03 83
84 DS612F4 84
SPI 1 Address: 0x06 84
DS612F4 85 85
SPI 1 Address: 0x09 85
23.2 Digital Filter Registers 86
DS612F4 87 87
DF Address: 0x00 87
88 DS612F4 88
DF Address: 0x0E 88
DS612F4 89 89
DF Address: 0x0F 89
90 DS612F4 90
DF Address: 0x10 90
DS612F4 91 91
DF Address: 0x11 91
92 DS612F4 92
DF Address: 0x12 92
DS612F4 93 93
DF Address: 0x20 93
94 DS612F4 94
DF Address: 0x21 94
DS612F4 95 95
DF Address: 0x25 95
96 DS612F4 96
DF Address: 0x29 96
DS612F4 97 97
DF Address: 0x2A 97
98 DS612F4 98
DF Address: 0x2B 98
DS612F4 99 99
DF Address: 0x2C 99
100 DS612F4 100
DF Address: 0x2E 100
DS612F4 101 101
DF Address: 0x2F 101
24.PIN DESCRIPTIONS 102
64L TQFP PACKAGE DRAWING 105
26.ORDERING INFORMATION 106
28.REVISION HISTORY 106

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