Cirrus-logic CS53L30 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2013(All Rights Reserved)http://www.cirrus.comLow-Power Quad-Channel Microphone ADC with TDM OutputAnalog Input and ADC

10 DS992F1CS53L303 Characteristics and SpecificationsTable 3-5. Analog-Input-to-Serial-Port CharacteristicsTest conditions (unless otherwise specified

DS992F1 11CS53L303 Characteristics and SpecificationsTable 3-6. MIC BIAS CharacteristicsTest conditions (unless otherwise specified): Fig. 2-1 shows C

12 DS992F1CS53L303 Characteristics and SpecificationsTable 3-8. Power Consumption Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L3

DS992F1 13CS53L303 Characteristics and SpecificationsTable 3-9. Register Field SettingsUseCasesRegister Fields and SettingsPDN_ULPPDN_LPMCLK_DISMCLK_

14 DS992F1CS53L303 Characteristics and SpecificationsTable 3-10. Switching Specifications—Digital Mic InterfaceTest conditions (unless specified other

DS992F1 15CS53L303 Characteristics and SpecificationsTable 3-12. Switching Specifications—Time-Division Multiplexed (TDM) ModeTest conditions (unless

16 DS992F1CS53L303 Characteristics and Specifications8.Hand-off timing for multidevice systems (SHIFT_LEFT = 1). When SHIFT_LEFT = 1, it is recommende

DS992F1 17CS53L303 Characteristics and SpecificationsTable 3-14. Digital Interface Specifications and CharacteristicsTest conditions (unless specified

18 DS992F1CS53L304 Functional Description4 Functional DescriptionThis section provides a general description of the CS53L30 architecture and detailed

DS992F1 19CS53L304.2 ResetsThe CS53L30 consists of the following blocks:• Interrupts. The CS53L30 QFN package includes an open-drain, active-low inter

2 DS992F1CS53L30 General DescriptionThe CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic application

20 DS992F1CS53L304.4 Capture-Path Inputs4.3.2 Interrupt Handling with the QFN PackageThe interrupt pin (INT) is implemented on the QFN package. Interr

DS992F1 21CS53L304.4 Capture-Path InputsFig. 4-4 shows details of the various analog input gain settings, including control register fields.Figure 4-4

22 DS992F1CS53L304.4 Capture-Path InputsFigure 4-6. Fully Differential Mic Input Connections ExampleFig. 4-7 shows the IN1–IN4 interfaces and the rela

DS992F1 23CS53L304.5 Digital Microphone (DMIC) Interface4.4.2 External Coupling CapacitorsThe analog inputs are internally biased to the internally ge

24 DS992F1CS53L304.5 Digital Microphone (DMIC) Interface4.5.1 DMIC Interface DescriptionThe DMIC interface consists of a serial-data shift clock outpu

DS992F1 25CS53L304.6 Serial Ports4.6 Serial PortsThe CS53L30 has a highly configurable serial port to communicate audio and voice data to and from oth

26 DS992F1CS53L304.6 Serial Ports4.6.3 High-Impedance ModeThe serial port may be placed on a clock/data bus that allows multiple masters, without a ne

DS992F1 27CS53L304.6 Serial Ports4.6.5 Serial-Port Sample RatesTable 4-2 lists the supported sample rates. Before making changes to any clock setting

28 DS992F1CS53L304.6 Serial Ports4.6.6 I2S FormatI2S format offers the following:• Up to 24 bits/sample of stereo data can be transferred (see Section

DS992F1 29CS53L304.7 TDM ModeFigure 4-11. I2S Format4.6.6.1 I2S Format Bit DepthsI2S interface data word length (see Section 4.6.6) is ambiguous. Fort

DS992F1 3CS53L30 Table of Contents1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 WLCSP . . . . .

30 DS992F1CS53L304.7 TDM ModeFigure 4-13. TDM Format—ASP_SCLK_INV = 0, SHIFT_LEFT = 1Figure 4-14. TDM Format—SCLK_INV = 1, SHIFT_LEFT = 0Figure 4-15.

DS992F1 31CS53L304.7 TDM Mode4.7.2 Bursted SCLKAfter all the data is sent on the TDM bus, it is not necessary to continue to toggle SCLK for the remai

32 DS992F1CS53L304.7 TDM Mode4.7.3 Transmitting DataFig. 4-17 shows the TDM transmit subblock.Figure 4-17. TDM Transmit Subblock Diagram4.7.3.1 Transm

DS992F1 33CS53L304.8 Synchronous Sample-Rate Converter (SRC)To maximize bus usage, the device supports hand-off between devices in a half clock cycle,

34 DS992F1CS53L304.9 Multichip Synchronization Protocol4.9 Multichip Synchronization ProtocolDue to the multidrop capability of the CS53L30 TDM bus,

DS992F1 35CS53L304.12 MUTE PinTo use thermal overload notification, do the following:1. Enable the thermal-sense circuitry by programming THMS_PDN (se

36 DS992F1CS53L304.14 I2C Control PortAD0 and AD1 are the logic state of the ASP_SDOUT2/AD0 and DMIC2_SCLK/AD1 pins, which are pulled to the supply or

DS992F1 37CS53L304.15 QFN Thermal PadFigure 4-20. Control Port Timing, I2C Reads with Preamble and AutoincrementThe following pseudocode illustrates a

38 DS992F1CS53L305.1 Octal Microphone Array to the Audio Serial Port5.1 Octal Microphone Array to the Audio Serial PortFig. 5-1 shows connections for

DS992F1 39CS53L305.2 Power-Up SequenceThe CS53L30 includes a synchronization protocol that can be used to minimize channel-to-channel phase mismatch a

4 DS992F1CS53L301 Pin Descriptions1 Pin Descriptions1.1 WLCSPFigure 1-1. Top-Down (Through-Package) View—30-Ball WLCSP PackageIN1+/DMIC1_SDIN2+ IN3+/D

40 DS992F1CS53L305.2 Power-Up Sequence6.4 Configure TDM channels.ASP TDM TX Control 1–4, Address 0x0E–0x11ASP TDM TX Control 1, Address 0x0E 0x00ASP_C

DS992F1 41CS53L305.3 Power-Down Sequence5.3 Power-Down SequenceEx. 5-2 is a procedure for powering down the device.9.4 Configure the ADC2A and ADC2B p

42 DS992F1CS53L305.4 Capture-Path Inputs5.4 Capture-Path InputsThe CS53L30 capture-path inputs can accept either analog or digital sources. This secti

DS992F1 43CS53L305.4 Capture-Path InputsFigure 5-2. Differential Analog Input Signal to IN±, with Protection Diodes ShownFigure 5-3. Differential Anal

44 DS992F1CS53L305.5 MCLK Jitter5.5 MCLK JitterThe following analog and digital specifications listed in Section 3 are affected by MCLK jitter:• INx-t

DS992F1 45CS53L306 Register Quick Reference6 Register Quick ReferenceDefault values are shown below the bit names.Adr. Function765432100x00 Reserved —

46 DS992F1CS53L306 Register Quick Reference0x1B LRCK Control 1 LRCK_TPWH[10:3]p. 51 000000000x1C LRCK Control 2 — LRCK_50_NPW LRCK_TPWH[2:0]p. 51 0000

DS992F1 47CS53L307 Register Descriptions7 Register DescriptionsAll registers are read/write except for the chip ID, revision register, and status regi

48 DS992F1CS53L307.6 MCLK Control5 DISCHARGE_FILT+Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this

DS992F1 49CS53L307.8 Mic Bias Control7.8 Mic Bias ControlAddress 0x0AR/W76543210MIC4_BIAS_PDN MIC3_BIAS_PDN MIC2_BIAS_PDN MIC1_BIAS_PDN— VP_MIN MIC_BI

DS992F1 5CS53L301.2 QFN1.2 QFNFigure 1-2. Top-Down (Through-Package) View—32-Pin QFN Package1.3 Pin DescriptionsTable 1-1. Pin DescriptionsNameBall#P

50 DS992F1CS53L307.11 ASP TDM TX Control 1–47.11 ASP TDM TX Control 1–4Address 0x0E–0x11R/W7 6543210ASP_CHx_TX_STATE— ASP_CHx_TX_LOC[5:0]Default 0 0 1

DS992F1 51CS53L307.15 LRCK Control 17.15 LRCK Control 1Address 0x1BR/W76543210LRCK_TPWH[10:3]Default00000000Bits Name Description7:0 LRCK_TPWH[10:3]LR

52 DS992F1CS53L307.19 Input Bias Control 14 MUTE_ASP_SDOUT1_PDNPower down ASP_SDOUT1 when MUTE pin is asserted. Setting is ignored in TDM Mode.0 (Defa

DS992F1 53CS53L307.24 ADC1/DMIC1 Control 21DMIC1_SCLK_DIVDMIC1 clock divide ratio. Selects the divide ratio between the internal MCLK and the digital

54 DS992F1CS53L307.26 ADC1 Noise Gate Control7.26 ADC1 Noise Gate ControlAddress 0x28R/W76 5 43210ADC1B_NG ADC1A_NG ADC1_NG_BOOST ADC1_NG_THRESH[2:0]

DS992F1 55CS53L307.29 ADC2/DMIC2 Control 17.29 ADC2/DMIC2 Control 1Address 0x2DR/W76 5 432 1 0ADC2B_PDN ADC2A_PDN — DMIC2_PDN DMIC2_SCLK_DIV —Default

56 DS992F1CS53L307.32 ADC2 Noise Gate Control7.32 ADC2 Noise Gate ControlAddress 0x30R/W76 5 43210ADC2B_NG ADC2A_NG ADC2_NG_BOOST ADC2_NG_THRESH[2:0]

DS992F1 57CS53L307.35 Device Interrupt Mask7.35 Device Interrupt MaskAddress 0x35R/W76543210M_PDN_DONE M_THMS_TRIPM_SYNC_DONEM_ADC2B_OVFLM_ADC2A_OVFLM

58 DS992F1CS53L308 Parameter Definitions8 Parameter Definitions9Plots9.1 Digital Filter Response9.1.1 ADC High-Pass FilterDynamic range. The ratio of

DS992F1 59CS53L309.1 Digital Filter Response9.1.2 Combined ADC and SRC Response, Fsext = FsintFigure 9-3. Passband—ADCx, Notch Enabled Figure 9-4. Sto

6 DS992F1CS53L301.3 Pin DescriptionsMIC_BIAS_FILT D6 15 VP I Microphone Bias Voltage Filter. Filter connection for the internal quiescent voltage used

60 DS992F1CS53L309.1 Digital Filter Response9.1.3 Combined ADC and SRC Response, Fsext = 50 kHz, Fsint = 16 kHz, MCLK = 19.2 MHzFigure 9-9. Transition

DS992F1 61CS53L309.1 Digital Filter Response9.1.4 Combined DMIC and SRC Response, Fsext = FsintFigure 9-15. Passband—ADCx, Notch Disabled Figure 9-16.

62 DS992F1CS53L309.2 PGA Gain Linearity9.2 PGA Gain LinearityFigure 9-21. Transition Band—DMICx, Notch Disabled Figure 9-22. Phase Response—DMICx, No

DS992F1 63CS53L309.3 Dynamic Range Versus Sampling Frequency9.3 Dynamic Range Versus Sampling Frequency9.4 FFTsFigure 9-25. Dynamic Range Versus Samp

64 DS992F1CS53L309.4 FFTsFigure 9-28. FFT, 1 kHz, –1 dBFS, Preamp Setting: +10 dB,PGA Setting: 0 dB, Fsint = Fsext = 48 kHzFigure 9-29. FFT, 1 kHz, –1

DS992F1 65CS53L3010 Package Dimensions10 Package Dimensions10.1 WLCSP PackageFigure 10-1. 30-Ball WLCSP Package Drawing Table 10-1. WLCSP Package Dim

66 DS992F1CS53L3010.2 QFN Package10.2 QFN PackageFigure 10-2. 32-Pin QFN Package Drawing 111 Thermal Characteristics12 Ordering InformationDimMillimet

DS992F1 67CS53L3013 Revision History13 Revision HistoryRevision ChangeF1 • Provided specific range of audio sample rates in System Features section o

DS992F1 7CS53L302 Typical Connection Diagram2 Typical Connection DiagramFigure 2-1. Typical Connection Diagram—Analog Microphone ConnectionsDMIC2_SCLK

8 DS992F1CS53L302 Typical Connection DiagramFigure 2-2. Typical Connection Diagram—Digital Microphone Connections1. The MICx_BIAS compensation capacit

DS992F1 9CS53L303 Characteristics and Specifications3 Characteristics and SpecificationsSection 8 provides additional details about parameter definiti