Cirrus-logic CS5460A Instrukcja Użytkownika

1Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comCS5460ASingle Phase, Bi-directional Power/Energy ICFea

CS5460A10 DS487F5CSSCLKMSB MSB - 1LSBt2t1t3SDIMSB MSB - 1LSBCommand Time 8 SCLKsLSBt6MSB MSB - 1LSBMSB MSB - 1High Byte Mid Byte Low Bytett45SDI Write

CS5460ADS487F5 11RESSDISCLKt8t14t13t11t10SDOCSt5t4Data from EEPROM(Output)(Output)(Output)(Input)MODE(Input)t12t15t16STOPBITLAST 8 BITS(Input)t17Figur

CS5460A12 DS487F52. OVERVIEWThe CS5460A is a CMOS monolithic power mea-surement device with a real power/energy compu-tation engine. The CS5460A comb

CS5460ADS487F5 13Figure 3) will be enabled on the other channel; inorder to preserve the relative phase relationshipbetween the voltage-sense and curr

CS5460A14 DS487F5full-scale. Note that the 24-bit signed output wordsare expressed in two’s complement format. The24-bit data words in the CS5460A out

CS5460ADS487F5 15a 4.096 MHz clock at XIN, and K = 1, instanta-neous A/D conversions for voltage, current, andpower are performed at a 4000 Sps rate,

CS5460A16 DS487F5result from one of several result registers. The first8 SCLKs are used to clock in the command to de-termine which register is to be

CS5460ADS487F5 17complete isolation from the power lines. This isola-tion is achieved using three transformers. Onetransformer is a general-purpose vo

CS5460A18 DS487F5 VA+VD+0.1µF200µF200N1014VIN+9VIN-IIN-101516IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDISDOSCLKINTED

CS5460ADS487F5 19VA+ VD+0.1 µF100 µF500470 nF500NR3R4RBurden1014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDSDOSCLKI

CS5460A2 DS487F5TABLE OF CONTENTS 1. CHARACTERISTICS & SPECIFICATIONS ...

CS5460A20 DS487F5VA+ VD+CS5460A0.1 µF1k235nF500R1R21014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDISDOSCLKINTEDIREO

CS5460ADS487F5 213. FUNCTIONAL DESCRIPTION3.1 Pulse-Rate OutputAs an alternative to reading the real energythrough the serial port, the EOUT and EDI

CS5460A22 DS487F5EXAMPLE #2: The required number of pulses perunit energy present at EOUT is specified to be500 pulses/kW-hr; given that the maximumli

CS5460ADS487F5 23sented by one pulse, the CS5460A will issue a“burst” of one or more pulses on EOUT (and alsopossibly on EDIR). The CS5460A will issue

CS5460A24 DS487F5pulse, one of the output pins (either EOUT or ED-IR) changes state. When the CS5460A must issueanother energy pulse, the other output

CS5460ADS487F5 25or custom calibration board. When the meteringsystem is installed, the calibrator would be used tocontrol calibration and/or to progr

CS5460A26 DS487F53.3.3 Application Note AN225For more information on Auto-boot mode, see theAN225, “USING THE CS5460A AUTO-BOOTMODE”.3.4 Interrupt a

CS5460ADS487F5 27that the Energy Register is read at least once in ev-ery 5 second span.3.5 Oscillator CharacteristicsXIN and XOUT are the input and

CS5460A28 DS487F5is explained in more detail in the following para-graphs).3.8.2 The Calibration RegistersRefer to Figure 3 and Figure 21.Voltage Cha

CS5460ADS487F5 29Note that when the calibration command is sent tothe CS5460A, the device must not be performingA/D conversions (in either of the two

CS5460ADS487F5 33.8.7.4 DC Gain Calibration Sequence ... 313.8.8 Duration of Calibration Seque

CS5460A30 DS487F5pins of the voltage/current channels to their groundreference level. (See Figure 17.) Offset and gain calibration cannot be done at t

CS5460ADS487F5 313.8.7.2 DC Offset Calibration SequenceThe Voltage Channel DC Offset Register holds thenegative of the simple average of N samples ta

CS5460A32 DS487F5age channel’s analog input signal with respect tothe current channel’s analog input signal.With the default setting, the phase delay

CS5460ADS487F5 33The voltage/current-channel inputs havesurge-current limits of 100 mA. This applies to briefvoltage/current spikes (<250 ms). The

CS5460A34 DS487F53.13 Input FilteringFigure 6 shows how the analog inputs can be con-nected for a single-ended input configuration. Notehere that the

CS5460ADS487F5 35Note also that in addition to the time-constants ofthe input R-C filters, the phase-shifting propertiesof the voltage/current sensors

CS5460A36 DS487F5b) The common-mode rejection performance of theCS5460A is sufficient within the frequency rangeover which the CS5460A performs A/D co

CS5460ADS487F5 37performed on each individual power meter, duringfinal calibration/test of the meter.3.14 Protection Against High-voltage and/or High

CS5460A38 DS487F5lution, because these resistors will dissipate whatcan be a significant amount of power, and they willcause an undesirable voltage dr

CS5460ADS487F5 394.1 Commands (Write Only)All command words are 1 byte in length. Commands that write to a register must be followed by 3 bytes of re

CS5460A4 DS487F5LIST OF FIGURESFigure 1. CS5460A Read and Write Timing Diagrams... 10Fi

CS5460A40 DS487F54.1.5 Power-Down The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except

CS5460ADS487F5 414.1.7 Register Read/Write This command informs the state machine that a register access is required. On reads the addressed regist

CS5460A42 DS487F54.2 Serial Port InterfaceThe CS5460A’s slave-mode serial interface con-sists of two control lines and two data lines, whichhave the

CS5460ADS487F5 43slow rise times and/or noisy control signals. (It isnot uncommon to experience temporary periods ofabnormally high noise and/or slow,

CS5460A44 DS487F55. REGISTER DESCRIPTIONS Note: 1. ** “default” => bit status after software or hardware reset2. Note that all registers

CS5460ADS487F5 45RS Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by

CS5460A46 DS487F55.2 Current Channel DC Offset Register and Voltage Channel DC Offset RegisterAddress: 1 (Current Channel DC Offset Register)3 (Volt

CS5460ADS487F5 475.5 Pulse-Rate Register Address: 6 Default** = 32000.00HzThe Pulse-Rate Register determines the frequency of the train of pulses out

CS5460A48 DS487F55.9 Power Offset RegisterAddress: 14 Default** = 0.000This offset value is added to each power value that is computed for each volta

CS5460ADS487F5 49allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.IC Invalid Command. No

CS5460ADS487F5 51. CHARACTERISTICS & SPECIFICATIONSANALOG CHARACTERISTICS(TA= -40 °C to +85 °C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGN

CS5460A50 DS487F5CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz.EDIR Se

CS5460ADS487F5 516. PIN DESCRIPTIONS 1234567817181920212223249101112 13141516Crystal Out XOUTCPU Clock Output CPUCLKPositive Digital Supply VD+Digit

CS5460A52 DS487F5Voltage Reference Output11 VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magni

CS5460ADS487F5 537. PACKAGE DIMENSIONSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

CS5460A54 DS487F58. ORDERING INFORMATION 9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified

CS5460A6 DS487F5ANALOG CHARACTERISTICS (Continued)Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value.8. All outputs unlo

CS5460ADS487F5 7VREFOUT REFERENCE OUTPUT VOLTAGENotes: 12. The voltage at VREFOUT is measured across the temperature range. From these measurements th

CS5460A8 DS487F53.3 V DIGITAL CHARACTERISTICS(TA=-40°C to +85°C; VA+=5V±10%, VD+=3.3V±10%; VA-, DGND = 0 V) (See Notes 3, 4, and 13)Notes: 15. All mea

CS5460ADS487F5 9SWITCHING CHARACTERISTICS(TA= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 =