Cirrus-logic CDB5460AU Instrukcja Użytkownika

Copyright © Cirrus Logic, Inc. 2009(All Rights Reserved)www.cirrus.comCDB5460AUCDB5460AU Evaluation Board and SoftwareFeatures Voltage and Current In

CDB5460AU10 DS487DBU1If the Data from Disk item in the Setup menu is selected, a file selection window will appear as shown inFigure 5. User can selec

CDB5460AUDS487DBU1 112.3.3 Quit MenuThe Quit menu allows the user to exit the evaluation software. Upon selecting Quit, a message windowappears and qu

CDB5460AU12 DS487DBU12.4 Setup WindowThe evaluation software provides access to the CS5460A's internal registers through the Setup window.See Fig

CDB5460AUDS487DBU1 132.4.3 CS5460A Crystal FrequencyThe CS5460A accepts a wide range of crystal input frequencies, and can therefore run at many diffe

CDB5460AU14 DS487DBU12.5 Calibration WindowThe Calibration window is used to display and write to the CS5460A offset and gain calibration registers.Th

CDB5460AUDS487DBU1 152.5.2.1 Offset Calibrations1. Ground the channel(s) you want to calibrate directly at the channel header(s), J17 and J22 for the

CDB5460AU16 DS487DBU12.6 Conversion WindowThe Conversion window allows the user to see the results of single and continuous conversions, performdata a

CDB5460AUDS487DBU1 172.6.4 Power Up ButtonThis button is used to send the Power Up/Halt command to the CS5460A. The part will return to normaloperatin

CDB5460AU18 DS487DBU12.8 Data Collection WindowThe Data Collection window (Figure 12) allows the user to collect sample sets of data from the CS5460Aa

CDB5460AUDS487DBU1 192.8.4 Output ButtonThis button will bring up a window in which the user can output the collected data to a file for later use,pri

CDB5460AU2 DS487DBU1TABLE OF CONTENTS1. HARDWARE ...

CDB5460AU20 DS487DBU12.8.7.3 FFT WindowThis field allows the user to select the type of windowing algorithm for FFT processing. Windowing algo-rithms

CDB5460AUDS487DBU1 212.8.10 Analyzing DataThe evaluation software provides three types of analysis tests: Time Domain, Frequency Domain, andHistogram.

CDB5460AU22 DS487DBU12.8.11.3 MEANIndicates the mean of the data sample set. The mean is calculated using the following formula:2.8.11.4 STD_DEVIndica

CDB5460AUDS487DBU1 232.8.12 Frequency Domain InformationThe following describe the indicators associated with FFT (Fast Fourier Transform) analysis. F

CDB5460AU24 DS487DBU12.8.12.6 SNRIndicates for the signal-to-noise ratio, first 4 harmonics are not included (decibels).2.8.12.7 FS-PdbIndicates for t

CDB5460AUDS487DBU1 252.9 EEPROM WindowCDB5460AU has an "Auto-Boot" demo feature that uses the on-board serial EEPROM, so that theCDB5460AU c

CDB5460AU26 DS487DBU12.10 Debug PanelThe Debug panel provides the user a way to access CS5460A registers and send commands to CS5460Adirectly. See Fig

CDB5460AUDS487DBU1 27APPENDIX A. BILL OF MATERIALS CIRRUS LOGICCDB5460AU_Rev_B.bomBILL OF MATERIAL (Page 1 of 2)Item Cirrus P/N Rev Description Q

CDB5460AU28 DS487DBU1 CIRRUS LOGICCDB5460AU_Rev_B.bomBILL OF MATERIAL (Page 2 of 2)Item Cirrus P/N Rev Description Qty Reference Designator MFG MFG P/

CDB5460AUDS487DBU1 29APPENDIX B. SCHEMATICS Figure 19. Schematic - Analog Inputs

CDB5460AUDS487DBU1 31. HARDWARE1.1 IntroductionThe CDB5460AU evaluation board provides a quick means of evaluating the CS5460A power measure-ment IC.

CDB5460AU30 DS487DBU1 Figure 20. Schematic - CS5460A & Socket

CDB5460AUDS487DBU1 31 Figure 21. Schematic - Microcontroller & USB Interface

CDB5460AU32 DS487DBU1 Figure 22. Schematic - Power Supplies

CDB5460AUDS487DBU1 33APPENDIX C. LAYER PLOTS Figure 23. Top Silkscreen

CDB5460AU34 DS487DBU1 Figure 24. Top Routing

CDB5460AUDS487DBU1 35 Figure 25. Bottom Routing

CDB5460AU36 DS487DBU1 Figure 26. Bottom Silkscreen

CDB5460AUDS487DBU1 37REVISION HISTORY Revision Date ChangesDB1 JAN 2009 Initial Release.

CDB5460AU38 DS487DBU1Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the o

CDB5460AU4 DS487DBU11.3 Analog SectionThe CDB5460AU evaluation board provides screw-type terminals (J23, J27) to connect input signals to the voltagea

CDB5460AUDS487DBU1 5are connected to analog ground (AGND). With a jumper on J17, J22, J24, and J26 in position VREF, the inputs areconnected to the re

CDB5460AU6 DS487DBU1for the 8051 microcontroller (8051_REGIN). Jumper J9 allows the 8051_REGIN supply to be sourcedfrom either the Vu+_EXT binding pos

CDB5460AUDS487DBU1 7The EEPROM must be programmed prior to the auto-boot sequence. When the CDB5460AU EvaluationBoard is sent from the factory, the EE

CDB5460AU8 DS487DBU12. SOFTWAREThe evaluation board comes with software and an USB cable to link the evaluation board to the PC. Theevaluation softwar

CDB5460AUDS487DBU1 92.3.1 Setup MenuSetup allows user to establish a USB communication connection with CDB5460AU board or select a pre-viously saved d