Cirrus-logic CS5368 Instrukcja Użytkownika Pobierz pdf (Strona 18)

18 DS624F5

CS5368

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING

Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C

=30pF

Notes:

1. Data must be held for sufficient time to bridge the transition time of CCLK.

2. For f

sck

<1 MHz

Figure 6. SPI Timing

Parameter Symbol Min Max Units

CCLK Clock Frequency f

sck

06.0MHz

RST

Rising Edge to CS Falling t

srs

Falling to CCLK Edge t

css

CS High Time Between Transmissions t

csh

1.0 s

CCLK Low Time t

scl

CCLK High Time t

sch

CDIN to CCLK Rising Setup Time t

dsu

CCLK Rising to DATA Hold Time (Note 1) t

CCLK Falling to CDOUT Stable t

Rise Time of CDOUT t

Fall Time of CDOUT t

Rise Time of CCLK and CDIN (Note 2) t

100

Fall Time of CCLK and CDIN (Note 2) t

CCLK

CDIN

CDOUT

RST

srs

scl

sch

css

csh

dsu

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 41 42

Features 1
Description 2
TABLE OF CONTENTS 3
LIST OF FIGURES 4
LIST OF TABLES 5
1. PIN DESCRIPTION 6
DS624F5 7 7
Stand-Alone Mode 7
8 DS624F5 8
Control Port Mode 8
DS624F5 9 9
ABSOLUTE RATINGS 10
SYSTEM CLOCKING 10
DC POWER 11
LOGIC LEVELS 11
100 - ppm/°C 12
OVERFLOW TIMEOUT 14
4. APPLICATIONS 19
4.3 Master Clock Source 20
SCLK & LRCK/FS 21
4.5.1 I²S and LJ Format 22
4.5.2 TDM Format 23
4.6 Speed Modes 23
4.6.1 Sample Rate Ranges 23
MCLK DIVIDERS 24
SAMPLE RATE DIVIDERS 24
26 DS624F5 26
TDM MASTER DSM Fs = 96 kHz 26
TDM SLAVE DSM Fs = 96 kHz 26
TDM MASTER QSM Fs = 192 kHz 26
TDM SLAVE QSM Fs = 192 kHz 26
4.8 Reset 27
4.8.1 Power-Down Mode 27
4.9 Overflow Detection 27
4.10 Analog Connections 28
4.12 DC Offset Control 29
4.13 Control Port Operation 30
4.13.1 SPI Mode 30
4.13.2 I²C Mode 31
5. REGISTER MAP 32
5.7 05h Reserved 34
5.9 07h Reserved 34
5.11 09h Reserved 35
6. FILTER PLOTS 36
DS624F5 37 37
38 DS624F5 38
7. PARAMETER DEFINITIONS 39
8. PACKAGE DIMENSIONS 40
THERMAL CHARACTERISTICS 40
48L LQFP PACKAGE DRAWING 40
9. ORDERING INFORMATION 41
10.REVISION HISTORY 41

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