Cirrus-logic CDB5364 Instrukcja Użytkownika

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS5364Features! Single-Ended to Differential Analog

10 DS625DB1CDB53644.2 SwitchesThe CDB5364 Evaluation Board switches are used for setting speed modes and format protocols and forresetting devices to

DS625DB1 11CDB53644.5 Power Supply CircuitryPower is applied to the evaluation board through five binding posts (+5 V, +12 V, -12 V, VA and GND). TheG

12 DS625DB1CDB53645. SCHEMATICS Figure 4. CS5364 (Schematic page 1)

DS625DB1 13CDB5364 Figure 5. Clock Generation (Schematic page 2)

14 DS625DB1CDB5364 Figure 6. FPGA (Schematic page 3)

DS625DB1 15CDB5364 Figure 7. Control Port (Schematic page 4)

16 DS625DB1CDB5364 Figure 8. Clock and Data Buffers (Schematic page 5)

17 DS625DB1CDB5364 Figure 9. CD8406 S/PDIF Output (Schematic page 6)

DS625DB1 18CDB5364 Figure 10. Analog Inputs 1 to 4 (Schematic page 7)

19 DS625DB1CDB5364 Figure 11. Analog Inputs 5 to 8 (Schematic page 8)

2 DS625DB1CDB5364TABLE OF CONTENTS1. CDB5364 System Overview...

DS625DB1 20CDB5364 Figure 12. Power (Schematic page 9)

21 DS625DB1CDB53646. BOARD LAYOUT AND ROUTING PLOTS Figure 13. Top Silkscreen

22 DS625DB1CDB5364 Figure 14. Top Layer

DS625DB1 23CDB5364 Figure 15. Bottom Layer

24 DS625DB1CDB53647. REVISION HISTORY Release Date ChangesDB1 September 2005 Initial ReleaseContacting Cirrus Logic SupportFor all product questions

DS625DB1 3CDB53641. CDB5364 SYSTEM OVERVIEWThe CDB5364 Evaluation Board provides an excellent means of quickly evaluating the CS5364. A digital audio

4 DS625DB1CDB53643.1.1 S1 and S4 Switch OperationDIP Switch S1 contains six switches that function as described below.M1,M0 set the device Speed Mode

DS625DB1 5CDB53643.2 Control-Port EvaluationThe CDB5364 is shipped with a Cirrus Logic designed Microsoft Windows-based program that allows fullcontro

6 DS625DB1CDB53643.3 FlexGUI Hi-Level ViewThe Cirrus Logic FlexGUI defaults to the Hi-Level View as shown in Figure 1. This view provides functionally

DS625DB1 7CDB53643.4 FlexGUI Low-Level ViewThe Low-level Register Map view provides direct control over the CS5364, the FPGA and GPIO settingsthat cha

8 DS625DB1CDB53643.5 Bit Definitions3.5.1 CS5364 BitsThe Low-Level view of the FlexGUI provides the full register set of the CS5364 under the CS5364 t

DS625DB1 9CDB5364In TDM mode, SDOUT_SEL1 and SDOUT_SEL 0 extract two stereo pairs from the CS5364 TDM stream,convert the data to Left-Justified PCM fo