Cirrus-logic CS4297A Instrukcja Użytkownika

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CS4297A102. GENERAL DESCRIPTIONThe CS4297A is a mixed-signal serial audio Codeccompliant to the Intel® Audio Codec ‘97 Specifica-tion, revision 2.1 [1

CS4297A11data in its Slot 2. Write operations are similar, withthe register index in Slot 1 and the write data in Slot2 of a SDATA_OUT frame. The func

CS4297A12VOLMUTEVOLMUTEVOLMUTEVOL VOLMUTEVOL VOL VOLMUTEBOOSTΣ ΣΣ1/2OUTPUTBUFFEROUTPUTBUFFEROUTPUTBUFFERVOL VOLADCINPUTMUXVOLADCMUTEPCM_OUTPC_BEEPPHON

CS4297A133. AC LINK FRAME DEFINITIONThe AC-link is a bidirectional serial port with dataorganized into frames consisting of one 16-bit andtwelve 20-bi

CS4297A143.1 AC-Link Serial Data Output FrameIn the serial data output frame, data is passed on the SDATA_OUT pin to the CS4297A from the AC ’97contro

CS4297A153.1.2 Command Address Port (Slot 1)R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index bits

CS4297A163.2 AC-Link Audio Input FrameIn the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC ’97 con-troller. T

CS4297A173.2.3 Status Data Port (Slot 2)RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous

CS4297A183.3 AC-Link Protocol Violation - Loss of SYNCThe CS4297A is designed to handle SYNC proto-col violations. The following are situations wheret

CS4297A194. REGISTER INTERFACE Reg Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default00h Reset 0 SE4 SE3 SE2 SE1 SE0 0 ID8

CS4297A2TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...5Analog Characterist

CS4297A204.1 Reset Register (Index 00h) SE[4:0] Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present.ID8 18-bit ADC Res

CS4297A214.3 Alternate Volume Register (Index 04h) Mute Alternate Mute. Setting this bit mutes the ALT_LINE_OUT_L/R output signals.ML[4:0] Alternate V

CS4297A224.5 PC_BEEP Volume Register (Index 0Ah) Mute PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal.PV[3:0] PC_BEEP Volume Control. Th

CS4297A234.7 Microphone Volume Register (Index 0Eh)Mute Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or

CS4297A244.8 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h)Mute Stereo Input Mute. Setting this bit mutes the respective input signal, bot

CS4297A254.9 Input Mux Select Register (Index 1Ah)SL[2:0] Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for

CS4297A264.11 General Purpose Register (Index 20h)3D 3D Enable. When ‘set’, the 3D bit enables the CrystalClearTM 3D stereo enhancement. This function

CS4297A274.13 Powerdown Control/Status Register (Index 26h)EAPD External Amplifier Power Down. The EAPD pin follows this bit and is generally used to

CS4297A284.14 Extended Audio ID Register (Index 28h)ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When ID

CS4297A294.17 AC Mode Control Register (Index 5Eh)DDM DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. Whe

CS4297A34.10 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ...244.11 Input Mux Select Register (Index 1Ah

CS4297A304.19 S/PDIF Control Register (Index 68h)SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin. The SPEN b

CS4297A314.20 Vendor ID1 Register (Index 7Ch)F[7:0] First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII ‘C’ charac

CS4297A325. POWER MANAGEMENT5.1 AC ’97 Reset ModesThe CS4297A supports three reset methods, as de-fined in the AC ’97 Specification: Cold AC ’97 Re-se

CS4297A335.2 Powerdown ControlsThe Powerdown Control/Status Register(Index 26h) controls the power management func-tions. The PR[6:0] bits in this re

CS4297A34PR Bit ADCs DACs MixerAlternate Line OutAnalog ReferenceACLinkInternal Clock Off PR0•PR1 •PR2 •• •PR3 ••• • •PR4 •PR5 ••• • • • •PR6 •Table 1

CS4297A356. ANALOG HARDWARE DESCRIPTIONThe analog line-level input hardware consists offour stereo inputs (LINE_IN_L/R, CD_L/GND/R,VIDEO_L/R, and AUX_

CS4297A366.1.3 Microphone Inputs Figure 13 illustrates an input circuit suitable for dy-namic and electret microphones. Electret, or phan-tom-powered,

CS4297A376.1.5 Phone InputOne application of the PHONE input is to interfaceto the output of a modem analog front end (AFE)device so that modem dialin

CS4297A386.3 Miscellaneous Analog Signals The AFLT1 and AFLT2 pins must have a 1000 pFNPO capacitor to analog ground. These capacitorsprovide a single

CS4297A397. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF)The S/PDIF digital output is used to interface theCS4297A to consumer audio equipment external toth

4 DS318PP6CS4297ACS4297A4Figure 11. Differential 2 VRMS CD Input ...35Fig

CS4297A40 AnalogGroundPin 10.1 µF1000 pFNPO1µF0.1 µFY5V0.1 µFY5VY5V0.1 µFY5VAVdd2AVss2AFLT2REFFLTAVss1AVdd1DVdd2AFLT1DigitalGroundDVss2DVss1DVdd1Vr

CS4297A419. PIN DESCRIPTIONS CD_AUX_VIDEO_CD_MICPHONAUX_VIDEO_CD_GNMICLINE_IN_LINE_IN_LLLR2ERRD1LRBPCFGLINE_OUT_LFLTIAFLT1REFFLTLINE_OUT_RFLTOFLT3DAF

CS4297A42Audio I/OPC_BEEP - Analog Mono Source, Input, Pin 12The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to p

CS4297A43VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17These inputs form a stereo input pair to the CS4297A. It is intended to b

CS4297A44Analog Reference, Filters, and ConfigurationREFFLT - Internal Reference Voltage, Input, Pin 27This signal is the voltage reference used inter

CS4297A45AC-LinkRESET# - AC ’97 Chip Reset, Input, Pin 11This active low signal is the asynchronous Cold Reset input to the CS4297A. The CS4297A must

CS4297A4610. PARAMETER AND TERM DEFINITIONSAC ’97 SpecificationRefers to the Audio Codec ’97 Component Specification Ver 2.1 published by the Intel® C

CS4297A47Interchannel IsolationThe amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1kHz, 0 dB, signal

CS4297A4811. REFERENCE DESIGN R21R16 6.8KC3322pFNPOC3422pFNPOC71uFY5VC100.1uFX7RJ12X1HDR-SN/PB12C201uFY5VR14 6.8KC110.1uFX7RC40.1uFX7RR1 47KR6 6.8KC80

CS4297A4912. REFERENCES1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997http://www.cirrus.com/products/papers/meas/meas.html

CS4297A51. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V ±5

CS4297A5013. PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.055 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05 0.10 0.15B 0.007

• Notes •DS318PP6 51CS4297A

52 DS318PP6CS4297A52 DS318PP6CS4297A

CS4297A6MIXER CHARACTERISTICS (for CS4297A-KQZ only)ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)RECOMMENDED OPERATING CONDITIONS (A

CS4297A7AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load.

CS4297A8BIT_CLKTrst_lowTrst2clkTvdd2rst#VddRESET#Figure 1. Power Up TimingFigure 2. Codec Ready from Startup or Fault ConditionBIT_CLKTsync2crdCODEC

CS4297A9BIT_CLKTisetupTiholdTcoSDATA_OUT,SYNCSDATA_INFigure 4. Data Setup and HoldBIT_CLKTs2_pdownSDATA_INSDATA_OUTSYNCWrite to 0x20 Data PR4 Don’t C