Cirrus-logic CS42L51 Instrukcja Użytkownika

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.comJULY '06DS679F1Low Power, Stereo CODEC with Headphone AmpDIGITAL to

10 DS679F1CS42L512. TYPICAL CONNECTION DIAGRAMS 1 µF+1.8 V or +2.5 V1 µFVQDAC_FILT+0.1 µF1 µFDGNDVL0.1 µF+1.8 V, +2.5 Vor +3.3 VSCL/CCLKSDA/CDINRESET

DS679F1 11CS42L51+1.8V or +2.5V1 µFVQDAC_FILT+0.1 µF1 µFDGNDVL0.1 µF+1.8V, 2.5 Vor +3.3VI²S/LJMCLKDIV2RESETLRCKAGNDDEMMCLKSCLK0.1 µFVA_HPVD* Capacitor

12 DS679F1CS42L513. CHARACTERISTIC AND SPECIFICATION TABLES(All Min/Max characteristics and specifications are guaranteed over the Specified Operating

DS679F1 13CS42L51ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)(Test Conditions (unless otherwise specified): Input sine wave (relative to digital fu

14 DS679F1CS42L51ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale

DS679F1 15CS42L515. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table.6. Measured between AINxx a

16 DS679F1CS42L51ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)(Test conditions (unless otherwise specified): Input test signal is a full-scale 997

DS679F1 17CS42L51ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)(Test conditions (unless otherwise specified): Input test signal is a full-scale 997

18 DS679F1CS42L51LINE OUTPUT VOLTAGE CHARACTERISTICSTest conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave;

DS679F1 19CS42L51HEADPHONE OUTPUT POWER CHARACTERISTICSTest conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wav

2 DS679F1CS42L51SYSTEM FEATURES 24-bit Converters  4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation– Stereo Play

20 DS679F1CS42L51COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Notes:12. Response is clock dependent and will scale with Fs. Note th

DS679F1 21CS42L5114. After powering up the CS42L51, RESET should be held low after the power supplies and clocks aresettled.15. See “Example System C

22 DS679F1CS42L51SWITCHING SPECIFICATIONS - I²C® CONTROL PORT(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)19. Data must be held for sufficient t

DS679F1 23CS42L51SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT(Inputs: Logic 0 = DGND, Logic 1 = VL)20. Data must be held for sufficient time to bridg

24 DS679F1CS42L51DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) 22. The DC current draw represents the allowed curr

DS679F1 25CS42L51POWER CONSUMPTIONSee (Note 25)25. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =4

26 DS679F1CS42L514. APPLICATIONS4.1 Overview4.1.1 ArchitectureThe CS42L51 is a highly integrated, low power, 24-bit audio CODEC comprised of stereo an

DS679F1 27CS42L514.2 Hardware Mode A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Pow-er-Up Sequence”

28 DS679F1CS42L514.3 Analog InputsAINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-nals, all

DS679F1 29CS42L514.3.2 High-Pass Filter and DC Offset Calibration The high-pass filter continuously subtracts a measure of the DC offset from the outp

DS679F1 3CS42L51TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE ... 71.

30 DS679F1CS42L51The MICBIAS series resistor must be selected based on the requirements of the particular microphoneused. The MICBIAS output pin is se

DS679F1 31CS42L514.3.5 Analog Input MultiplexerA stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level inpu

32 DS679F1CS42L514.3.7 Automatic Level Control (ALC) When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when

DS679F1 33CS42L514.3.8 Noise GateThe noise gate may be used to mute signal levels that fall below a programmable threshold. This preventsthe ALC from

34 DS679F1CS42L514.4 Analog OutputsAOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing optionsare available,

DS679F1 35CS42L514.4.2 Volume ControlsThree digital volume control functions are implemented, offering independent control over the ADC andPCM signal

36 DS679F1CS42L514.4.5 Tone ControlShelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequen-cies. Bo

DS679F1 37CS42L514.4.7 Line-Level Outputs and FilteringThe CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outpu

38 DS679F1CS42L514.4.8 On-Chip Charge PumpAn on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dualrail suppl

DS679F1 39CS42L514.5.1 SlaveLRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined basedon the input MCLK/LRCK rat

4 DS679F1CS42L514.5.3 High-Impedance Digital Output ... 404

40 DS679F1CS42L514.5.3 High-Impedance Digital OutputThe serial port may be placed on a clock/data bus that allows multiple masters for the serial port

DS679F1 41CS42L51 4.7 InitializationThe initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC en-ters a Power-D

42 DS679F1CS42L514.9 Recommended Power-Down SequenceTo minimize audible pops when turning off or placing the CODEC in standby,1. Mute the DAC’s and AD

DS679F1 43CS42L514.10 Software ModeThe control port is used to access the registers allowing the CODEC to be configured for the desired oper-ational m

44 DS679F1CS42L51the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAPallows successive reads or wr

DS679F1 45CS42L514.10.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer t

46 DS679F1CS42L515. REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state.Addr

DS679F1 47CS42L51p60default0 00000000Eh Vol. Control ADCMIXAMUTE_ADCMIXAADCMIXAVOL6ADCMIXA VOL5ADCMIXA VOL4ADCMIXA VOL3ADCMIXA VOL2ADCMIXA VOL1ADCMIXA

48 DS679F1CS42L511Ah Limiter Con-fig & Release RateLIMIT_EN LIMIT_ALLLIM_RRATE5LIM_RRATE4LIM_RRATE3LIM_RRATE2LIM_RRATE1LIM_RRATE0p69default0 11111

DS679F1 49CS42L516. REGISTER DESCRIPTIONAll registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register whic

DS679F1 5CS42L5111. PARAMETER DEFINITIONS ...

50 DS679F1CS42L51Power Down PGA X (PDN_PGAX)Default: 00 - Disable1 - EnableFunction:PGA channel x will either enter a power-down or muted state when t

DS679F1 51CS42L51Speed Mode (SPEED[1:0])Default: 0111 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates10 - Half-Speed Mode (HSM) - 12.5 to 25 k

52 DS679F1CS42L516.4 Interface Control (Address 04h)SDOUT to SDIN Loopback (SDOUT->SDIN)Default: 00 - Disabled; SDOUT internally disconnected from

DS679F1 53CS42L51ADC I²S or Left-Justified (ADC_I²S/LJ)Default: 00 - Left-Justified1 - I²SFunction:Selects either the I²S or Left-Justified digital in

54 DS679F1CS42L51ADCx 20 dB Digital Boost (ADCx_DBOOST)Default: 00 - Disabled1 - EnabledFunction:Applies a 20 dB digital gain to the input signal on A

DS679F1 55CS42L51ADCX High-Pass Filter Freeze (ADCX_HPFRZ)Default: 00 - Continuous DC Subtraction1 - Frozen DC SubtractionFunction:The high-pass filte

56 DS679F1CS42L516.7 ADCx Input Select, Invert & Mute (Address 07h)ADCX Input Select Bits (AINX_MUX[1:0])Default: 00 Function:Selects the specifie

DS679F1 57CS42L516.8 DAC Output Control (Address 08h)Headphone Analog Gain (HP_GAIN[2:0])Default: 011 Function:These bits select the gain multiplier f

58 DS679F1CS42L516.9 DAC Control (Address 09h)DAC Data Selection (DATA_SEL[1:0])Default: 0000 - PCM Serial Port to DAC01 - Signal Processing Engine to

DS679F1 59CS42L51DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0]) Default = 1000 - Immediate Change01 - Zero Cross 10 - Soft Ramp11 - Soft Ramp on

6 DS679F1CS42L51LIST OF TABLESTable 1. I/O Power Rails ...

60 DS679F1CS42L51ALCX Zero Cross Disable (ALCX_ZCDIS)Default: 00 - Off1 - OnFunction:Overrides the ZCROSSx bit setting for the ADC. When this bit is s

DS679F1 61CS42L51Function:The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits(SOFTx & ZCROSSx)

62 DS679F1CS42L516.13 PCMX Mixer Volume Control:PCMA (Address 10h) & PCMB (Address 11h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b

DS679F1 63CS42L51Function:The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scaledirectly with sample

64 DS679F1CS42L51Function:The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-durationwill scale inversely

DS679F1 65CS42L51This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analogoutput. Note: Re-engaging the

66 DS679F1CS42L51Function:The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dBincrements from

DS679F1 67CS42L516.19 PCM Channel Mixer (Address 18h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this re

68 DS679F1CS42L51Cushion Threshold (CUSH[2:0]) Default: 000Function:Sets a cushion level below full scale. This setting is usually set slightly below

DS679F1 69CS42L516.21 Limiter Release Rate Register (Address 1Ah)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro

DS679F1 7CS42L511. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE Pin Name # Pin DescriptionLRCK1Left Right Clock (Input/Output) - Determines

70 DS679F1CS42L516.22 Limiter Attack Rate Register (Address 1Bh)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control

DS679F1 71CS42L516.24 ALC Release Rate (Address 1Dh)ALC Release Rate (RRATE[5:0])Default: 111111 Function:Sets the rate at which the ALC releases the

72 DS679F1CS42L51Function:Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate setin the release r

DS679F1 73CS42L51Function:Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96dB. NG_BOOST =

74 DS679F1CS42L516.28 Charge Pump Frequency (Address 21h)Charge Pump Frequency (CHRG_FREQ[3:0])Default: 0101Function:Alters the clocking frequency of

DS679F1 75CS42L517. ANALOG PERFORMANCE PLOTS7.1 Headphone THD+N versus Output Power PlotsTest conditions (unless otherwise specified): Input test sign

76 DS679F1CS42L51 G = 0.6047G = 0.7099G = 0.8399G = 1.0000G = 1.1430Legend-100-20-95-90-85-80-75-70-65-60-55-50-45-40-35-30dBr A0 60m6m 12m 18m 24

DS679F1 77CS42L517.2 Headphone Amplifier EfficiencyThe architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions

78 DS679F1CS42L517.3 ADC_FILT+ Capacitor Effects on THD+NThe value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic

DS679F1 79CS42L518. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled*The”MCLKDIV2” pin 4 must be set HI.Sample RateLRCK (kHz)MCLK (MHz)1024x 1

8 DS679F1CS42L51AOUTBAOUTA1011Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-tics specification

80 DS679F1CS42L518.2 Auto Detect Disabled Sample RateLRCK (kHz)MCLK (MHz)512x 768x 1024x 1536x 2048x 3072x8 - 6.1440 8.1920 12.2880 16.3840 24.576011.

DS679F1 81CS42L519. PCB LAYOUT CONSIDERATIONS9.1 Power Supply, GroundingAs with any high-resolution converter, the CS42L51 requires careful attention

82 DS679F1CS42L5110.ADC & DAC DIGITAL FILTERS Figure 34. ADC Passband Ripple Figure 35. ADC Stopband RejectionFigure 36. ADC Transition Band Fi

DS679F1 83CS42L5111.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

84 DS679F1CS42L5112.PACKAGE DIMENSIONS 1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies to the plated termin

DS679F1 85CS42L5113.ORDERING INFORMATION 14.REFERENCES1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Device

86 DS679F1CS42L5115.REVISION HISTORY Revision ChangesA1Initial ReleaseA2Renamed pin 14, FILT1+, to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+.Added 1.

DS679F1 87CS42L51PP1Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 12.Adjusted Ambient Operating Temp.

88 DS679F1CS42L51Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one

DS679F1 9CS42L511.1 Digital I/O Pin CharacteristicsThe logic level for each input should not exceed the maximum ratings for the VL power supply. Pin N