Cirrus-logic CDB42L56 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2014(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS42L56Features Analog Line and Microphone Level In

10 DS851DB1CDB42L563.2 PSIA In to Analog Out and Analog In to PSIA OutThe CS42L56 ADC and DAC performance can be tested by loading the “PSIA In to Ana

DS851DB1 11CDB42L564. SOFTWARE MODE CONTROLThe CDB42L56 may be used with the Microsoft® Windows®-based FlexGUI graphical user interface, allowing soft

12 DS851DB1CDB42L564.1 Board Configuration TabThe “Board Configuration” tab provides high-level control of signal routing on the CDB42L56. The control

DS851DB1 13CDB42L564.2 Codec Configuration TabThe “Codec Configuration” tab provides high-level control of the CS42L56 register settings. Status text

14 DS851DB1CDB42L564.3 Codec Analog Input Volume TabThe “Codec Analog Input Volume” tab provides high-level control of all volume settings in the ADC

DS851DB1 15CDB42L564.4 Codec DSP Engine TabThe “Codec DSP Engine” tab provides high-level control functions to modify the SDIN (PCM) data volumelevel,

16 DS851DB1CDB42L564.5 Codec Analog Output Volume TabThe “Codec Analog Output Volume” tab provides high-level control of the CS42L56 class H output am

17 DS851DB1CDB42L564.6 Register Maps TabThe Register Maps tab provides low-level control of the CS42L56, CS8416, CS8406, CS8421, FPGA andGPIO register

18 DS851DB1CDB42L565. JUMPER SETTINGS AND SYSTEM CONNECTIONS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENTEXT. +5V TP9 Input +5V power supply for evalua

19 DS851DB1CDB42L56 JMP LABEL PURPOSE POSITION FUNCTION SELECTEDJ31 VLSelects source of voltage for the VL supply*+1.8V Voltage source is +1.8 V regul

2 DS851DB1CDB42L56TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

20 DS851DB1CDB42L56J2 HPOUTA FLT/NOFLTSelects filtered or unfiltered output for HPOUTA*2 - 4, *1 - 3 Unfiltered output selected for HPOUTA. 4 - 6, 3 -

DS851DB1 21CDB42L566. PERFORMANCE PLOTSTest conditions (unless otherwise specified): TA= 25°C; VA=VCP=VLDO=VL=1.8 V; input test signal is a full-scale

22 DS851DB1CDB42L56-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS20 20k50 100 200 500 1k 2k 5k 10kHz-140+0-130-120-110-100-90-80-70-60-50-40-30

DS851DB1 23CDB42L56-110-70-108-106-104-102-100-98-96-94-92-90-88-86-84-82-80-78-76-74-72dBr A-60 +0-50 -40 -30 -20 -10dBr AMaster Volume (Digital)Head

24 DS851DB1CDB42L56-5+5-4.5-4-3.5-3-2.5-2-1.5-1-0.5+0+0.5+1+1.5+2+2.5+3+3.5+4+4.5dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-40+40-35-30-25-20-15-10-5+0+

DS851DB1 25CDB42L56-110-70-108-106-104-102-100-98-96-94-92-90-88-86-84-82-80-78-76-74-72dBr A-60 +0-50 -40 -30 -20 -10dBr AMaster Volume (Digital)Line

26 DS851DB1CDB42L56-5+5-4.5-4-3.5-3-2.5-2-1.5-1-0.5+0+0.5+1+1.5+2+2.5+3+3.5+4+4.5dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-40+40-35-30-25-20-15-10-5+0+

DS851DB1 27CDB42L567. CDB42L56 BLOCK DIAGRAM Figure 34. Block DiagramUSB µ controller CS42L56S/PDIF Rx (CS8416)S/PDIF Tx (CS8406)FPGAOscillator (sock

28 DS851DB1CDB42L568. CDB42L56 SCHEMATICSFigure 35. CS42L56 & Analog I/O (Schematic Sheet 1)

DS851DB1 29CDB42L56Figure 36. S/PDIF & Digital Interface (Schematic Sheet 2)

DS851DB1 3CDB42L56Figure 17. Fade-to-Noise Linearity - Analog In to Digital Out ... 22

30 DS851DB1CDB42L56Figure 37. PLL, oscillator and external I/O connections (Schematic Sheet 3)

DS851DB1 31CDB42L56Figure 38. Microcontroller and FPGA (Schematic Sheet 4)

DS851DB1 32CDB42L56Figure 39. Power (Schematic Sheet 5)

DS851DB1 33CDB42L569. CDB42L56 LAYOUTFigure 40. Silk Screen

DS851DB1 34CDB42L56Figure 41. Top-Side Layer

DS851DB1 35CDB42L56Figure 42. GND (Layer 2)

DS851DB1 36CDB42L56Figure 43. Power (Layer 3)

DS851DB1 37CDB42L56Figure 44. Bottom Side Layer

38 DS851DB1CDB42L5610.REVISION HISTORYRevision ChangesDB1 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inquiries, conta

4 DS851DB1CDB42L561. SYSTEM OVERVIEWThe CDB42L56 evaluation platform provides analog and digital interfaces to the CS42L56 and allows for externalDSP

DS851DB1 5CDB42L56Configuration of the CS8416 is made using controls in the “Board Configuration” tab of the Cirrus FlexGUIsoftware. Section 3. “Confi

6 DS851DB1CDB42L561.6 OscillatorThe socketed on-board oscillator (Y1) can be selected as the system master clock source by using the se-lections on th

DS851DB1 7CDB42L56Notes:1. Use headers J7 and J11 to select input signal ground reference (in pseudo-differential mode) as eitherthe CDB42L56 board gr

8 DS851DB1CDB42L562. QUICK-START GUIDEThe following figure is a simplified quick-start guide made for user convenience. The guide configures the board

DS851DB1 9CDB42L563. CONFIGURATION OPTIONSThis section shows two common configurations of the CDB42L56. 3.1 S/PDIF In to Analog Out and Analog In to S