Cirrus-logic CDB4265 Instrukcja Użytkownika Pobierz pdf (Strona 12)

CDB4265

12 DS657DB1

5. FPGA REGISTER DESCRIPTION

5.1 CODE REVISION ID - REGISTER 01H

Function:

Identifies the revision of the FPGA code. This register is Read-Only.

5.2 MCLK SOURCE CONTROL - ADDRESS 02H

5.2.1 MCLK SOURCE (BITS 5:4)

Default = 10

Function:

These bits select the source of the CS4265 MCLK signal. Table 1 shows the available settings.

76543210

Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0

76543210

Reserved Reserved MCLK1 MCLK0 Reserved Reserved Reserved Reserved

Table 1. MCLK Source

MCLK1 MCLK0 MCLK Source

0 0 Oscillator

0 1 MCLK position on PCM Header (J15)

1 0 CS8416 RMCK

11 Reserved

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 29 30

Brak uwag

Cirrus-logic CDB4265 Instrukcja Użytkownika Strona 12