Cirrus-logic CDB4265 Instrukcja Użytkownika

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCDB4265Evaluation Board for CS4265Featuresz Single-ended Analo

CDB426510 DS657DB13.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF OutUsing the pre-configured script file named “SPDIF Recovered Clock -

CDB4265DS657DB1 114. FPGA REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5432 1 001

CDB426512 DS657DB15. FPGA REGISTER DESCRIPTION5.1 CODE REVISION ID - REGISTER 01HFunction:Identifies the revision of the FPGA code. This register is R

CDB4265DS657DB1 135.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H5.3.1 SUBCLOCK SOURCE (BITS 1:0)Default = 01Function:This bit selects the source of the CS4

CDB426514 DS657DB15.4 CS4265 SDIN SOURCE CONTROL - ADDRESS 04H5.4.1 SDIN2 SOURCE (BITS 6:4)Default = 00Function:These bits select the source of the CS

CDB4265DS657DB1 155.5 TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H5.5.1 TXSDIN SOURCE (BITS 2:0)Default = 01Function:These bits select the source of

CDB426516 DS657DB16. CDB CONNECTORS, JUMPERS, AND SWITCHES CONNECTORReference Designator INPUT/OUTPUT SIGNAL PRESENT+5V J4 Input+5.0 V Power Supp

CDB4265DS657DB1 17 JUMPER PURPOSE POSITION FUNCTION SELECTEDJ6 Selects the source of voltage for the VLS supply.+1.8 V+2.5 V+3.3 V+5 V*Voltage source

CDB426518 DS657DB17. CDB BLOCK DIAGRAM CS4265Passive Input FilterActive Input FilterHeaderMicrophone InputS/PDIF Output CircuitsCannedOscill

CDB4265DS657DB1 198. CDB SCHEMATICS Figure 5. CS4265

CDB42652 DS657DB1TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

CDB426520 DS657DB1 Figure 6. Analog Inputs

CDB4265DS657DB1 21 Figure 7. Analog Outputs

CDB426522 DS657DB1 Figure 8. S/PDIF I/O

CDB4265DS657DB1 23 Figure 9. Control Port

CDB426524 DS657DB1 Figure 10. FPGA

CDB4265DS657DB1 25 Figure 11. Discrete Clock Routing and Level Shifting

CDB426526 DS657DB1 Figure 12. Power

CDB4265DS657DB1 279. CDB LAYOUT Figure 13. Silk Screen

CDB426528 DS657DB1 Figure 14. Topside Layer

CDB4265DS657DB1 29 Figure 15. Bottom side Layer

CDB4265DS657DB1 3LIST OF FIGURESFigure 1. CDB4265 Controls Tab...

CDB426530 DS657DB110.REVISION HISTORY Revision Date ChangesDB1 February 2005 Initial ReleaseTable 8. Revision HistoryContacting Cirrus Logic SupportFo

CDB42654 DS657DB11. SYSTEM OVERVIEW The CDB4265 evaluation board is an excellent means for evaluating the CS4265 CODEC. Analog and digital audiosignal

CDB4265DS657DB1 51.7 External Control HeadersThe evaluation board has been designed to allow interfacing with external systems via the headers J15, an

CDB42656 DS657DB12. SYSTEM CLOCKS AND DATAThe CDB4265 implements comprehensive clock and data routing capabilities. Configuration of the clock and dat

CDB4265DS657DB1 73. PC SOFTWARE CONTROLThe CDB4265 is shipped with a Microsoft Windows® based graphical user interface which allows control over theCS

CDB42658 DS657DB13.2 S/PDIF Rx Controls TabWhen the CDB4265 is configured to make use of the CS8416 S/PDIF receiver, these devices must be con-figured

CDB4265DS657DB1 93.3 Register Maps TabThe Register Maps tab provides low level control over the register level settings of the CS4265, CS8416,and FPGA