Cirrus-logic CS5381 Instrukcja Użytkownika Pobierz pdf (Strona 10)

10 DS563F2

CS5381

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT

(Logic “0” = GND = 0 V; Logic “1” = VL, C

L

= 20 pF)

Parameter Symbol Min Typ Max Unit

Output Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Fs

Fs

Fs

2

50

100

-

-

-

54

108

216

kHz

kHz

kHz

OVFL to LRCK Edge Setup Time

t

setup

16/f

sclk

--s

OVFL to LRCK Edge Hold Time

t

hold

1/f

sclk

--s

OVFL time-out on overrange condition

Fs = 44.1, 88.2, 176.4 kHz

Fs = 48, 96, 192 kHz

-

-

740

680

-

-

ms

ms

MCLK Specifications

MCLK Period

t

clkw

36 - 1953 ns

MCLK Duty Cycle

40 - 60 %

Master Mode

SCLK falling to LRCK transition

t

mslr

-20 - 20 ns

SCLK falling to SDOUT valid

t

sdo

- - 32 ns

SCLK Duty Cycle

-50-%

Slave Mode

Single-Speed

Output Sample Rate

Fs 2 - 54 kHz

LRCK Duty Cycle

40 50 60 %

SCLK Period

t

sclkw

145 - - ns

SCLK Duty Cycle

45 50 55 %

SDOUT valid before SCLK rising

t

stp

10 - - ns

SDOUT valid after SCLK rising

t

hld

5--ns

SCLK falling to LRCK transition

t

slrd

-20 - 20 ns

Double-Speed

Output Sample Rate

Fs 50 - 108 kHz

LRCK Duty Cycle

40 50 60 %

SCLK Period

t

sclkw

145 - - ns

SCLK Duty Cycle

45 50 55 %

SDOUT valid before SCLK rising

t

stp

10 - - ns

SDOUT valid after SCLK rising

t

hld

5--ns

SCLK falling to LRCK transition

t

slrd

-20 - 20 ns

Quad-Speed

Output Sample Rate

Fs 100 - 216 kHz

LRCK Duty Cycle

40 50 60 %

SCLK Period

t

sclkw

72 - - ns

SCLK Duty Cycle

45 50 55 %

SDOUT valid before SCLK rising

t

stp

10 - - ns

SDOUT valid after SCLK rising

t

hld

5--ns

SCLK falling to LRCK transition

t

slrd

-8 - 8 ns

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 23 24

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