Cirrus-logic CS5364 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2014(All Rights Reserved)http://www.cirrus.com114 dB, 192 kHz, 4-Channel A/D ConverterFeatures Advanced Multi-bit Delt

10 DS625F5CS53643. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSGND = 0 V, all voltages with respect to 0 V. 1. TDM Quad-Speed Mo

DS625F5 11CS5364DC POWERMCLK = 12.288 MHz; Master Mode. GND = 0 V. 1. Power-Down is defined as RST = LOW with all clocks and data lines held static at

12 DS625F5CS5364ANALOG CHARACTERISTICS (COMMERCIAL)Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full

DS625F5 13CS5364ANALOG PERFORMANCE (AUTOMOTIVE)Test Conditions (unless otherwise specified). VA = 5.25 to 4.75 V, VD = 5.25 to 3.14 V, VLS = VLC = 5.2

14 DS625F5CS5364DIGITAL FILTER CHARACTERISTICSNotes:1. The filter frequency response scales precisely with Fs.2. Response shown is for Fs equal to 48

DS625F5 15CS5364SERIAL AUDIO INTERFACE - I²S/LJ TIMINGThe serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.Logic "0&

16 DS625F5CS5364SERIAL AUDIO INTERFACE - TDM TIMINGThe serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.Logic "0&quo

DS625F5 17CS5364SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMINGInputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL=30pFNotes:1. Data must be held for s

18 DS625F5CS5364SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL=30pFNotes:1. Data must be held fo

DS625F5 19CS53644. APPLICATIONS4.1 PowerCS5364 features five independent power pins that power various functional blocks within the device andallow fo

2 DS625F5CS5364DescriptionThe CS5364 is a complete 4-channel analog-to-digital converter for digital audio systems. It performs sampling, an-alog-to-d

20 DS625F5CS53644.3 Master Clock SourceThe CS5364 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillatordriver o

DS625F5 21CS53644.4 Master and Slave OperationCS5364 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.See Se

22 DS625F5CS53644.5 Serial Audio Interface (SAI) FormatThe SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT

DS625F5 23CS53644.5.2 TDM FormatIn TDM Mode, all four channels of audio data are serially clocked out during a single Frame Sync (FS) cy-cle, as shown

24 DS625F5CS53644.6.3 Master Mode Clock DividersFigure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, i

DS625F5 25CS53644.7 Master and Slave Clock FrequenciesTables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The MC

26 DS625F5CS5364Table 9. Frequencies for 96 kHz Sample Rate using TDMTable 10. Frequencies for 96 kHz Sample Rate using TDMTable 11. Frequencies for 1

DS625F5 27CS53644.8 ResetThe device should be held in reset until power is applied and all incoming clocks are stable and valid. Uponde-assertion of R

28 DS625F5CS53644.10 Analog ConnectionsThe analog modulator samples the input at half of the internal Master Clock frequency, or 6.144 MHz nom-inally.

DS625F5 29CS53644.11 Optimizing Performance in TDM ModeNoise Management is a design technique that is utilized in the majority of audio A/D converters

DS625F5 3CS5364TABLE OF CONTENTS1. PIN DESCRIPTION ...

30 DS625F5CS53644.13 Control Port OperationThe Control Port is used to read and write the internal device registers. It supports two industry standard

DS625F5 31CS53644.13.2 I²C ModeIn I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

32 DS625F5CS53645. REGISTER MAPIn Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. Allr

DS625F5 33CS5364Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function isselected. When either bit i

34 DS625F5CS53645.6 04h (HPF) High-Pass Filter Register Default: 0x00, all high-pass filters enabled.The High-Pass Filter Register is used to enable

DS625F5 35CS53645.11 09h Reserved 5.12 0Ah (SDEN) SDOUT Enable Control Register Default: 0x00, all SDOUT pins enabled.The SDOUT Enable Control Regis

36 DS625F5CS53646. FILTER PLOTSFigure 19. SSM PassbandFigure 20. DSM PassbandFigure 21. QSM Passband0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−

DS625F5 37CS5364Figure 22. SSM StopbandFigure 23. DSM StopbandFigure 24. QSM Stopband0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91−140−120−100−80−60−40−20

38 DS625F5CS5364Figure 25. SSM -1 dB CutoffFigure 26. DSM -1 dB Cutoff Figure 27. QSM -1 dB Cutoff0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0

DS625F5 39CS53647. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

4 DS625F5CS53645.3 01h (GCTL) Global Mode Control Register ...325.4

40 DS625F5CS53648. PACKAGE DIMENSIONS THERMAL CHARACTERISTICS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.055 0.063 --- 1.40 1.60A1 0.002 0.

DS625F5 41CS53649. ORDERING INFORMATION10.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order #CS5364114dB, 192kHz,

42 DS625F5CS5364 Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one

DS625F5 5CS5364LIST OF TABLESTable 1. Power Supply Pin Definitions ...

6 DS625F5CS53641. PIN DESCRIPTION Figure 1. CS5364 Pinout DIF1/AD1/CDINREF_GNDAIN3+SDOUT1/TDMVLSTSTOGNDSDOUT2M0/SDA/CDOUTAIN1+AIN3-GNDGNDGNDGNDVDX

DS625F5 7CS5364 Pin Name Pin # Pin DescriptionAIN2+, AIN2-AIN4+, AIN4-AIN3+, AIN3-AIN1+, AIN1-1,211,1213,1447,48Differential Analog (Inputs) - Audio s

8 DS625F5CS5364Stand-Alone ModeCLKMODE 34CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device ci

DS625F5 9CS53642. TYPICAL CONNECTION DIAGRAM Figure 2. Typical Connection DiagramFor analog buffer configurations, refer to Cirrus Application Note A