Cirrus-logic CS42528 Instrukcja Użytkownika Strona 1

Copyright  Cirrus Logic, Inc. 2014 (All Rights Reserved)http://www.cirrus.com114 dB, 192-kHz 8-Ch CODEC with S/PDIF ReceiverFeatures Eight 24-bit D/

10 DS586F2CS42528D/A DIGITAL FILTER CHARACTERISTICS Notes:9. Response is clock dependent and will scale with Fs. Note that the response plots (Fig

DS586F2 11CS42528SWITCHING CHARACTERISTICS(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1

12 DS586F2CS42528SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inpu

DS586F2 13CS42528SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inp

14 DS586F2CS42528DC ELECTRICAL CHARACTERISTICS(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)Notes:23. Cu

DS586F2 15CS42528DIGITAL INTERFACE CHARACTERISTICS(TA = +25° C)Notes:27. Serial Port signals include: RMCK, OMCK, SAI_SCLK, SAI_LRCK, SAI_SDOUT, CX_SC

16 DS586F2CS425282. PIN DESCRIPTIONS Pin Name # Pin DescriptionCX_SDIN1CX_SDIN2CX_SDIN3CX_SDIN41646362Codec Serial Audio Data Inp

DS586F2 17CS42528INT11Interrupt (Output) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on pa

18 DS586F2CS42528OMCK59External Reference Clock (Input) - External clock reference that must be within the ranges specified in the register “OMCK Freq

DS586F2 19CS425283. TYPICAL CONNECTION DIAGRAM VDAOUTA1+240.1 µF+10 µF100 µF0.1 µF++1718VQFILT+36370.1 µF4.7 µFVA+10 µF51AOUTA1-AOUTB1+3534AOUTB1-

2 DS586F2CS42528TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

20 DS586F2CS425284. APPLICATIONS4.1 OverviewThe CS42528 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con-ve

DS586F2 21CS425284.2.2 High-Pass Filter and DC Offset CalibrationThe high-pass filter continuously subtracts a measure of the DC offset from the outpu

22 DS586F2CS425284.3.3 Digital Volume and Mute ControlEach DAC’s output level is controlled via the Volume Control registers operating over the range

DS586F2 23CS425284.4 S/PDIF ReceiverThe CS42528 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digitalaudio data a

24 DS586F2CS425284.5 Clock GenerationThe clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from theoutput of

DS586F2 25CS425284.5.2 OMCK System Clock ModeA special clock-switching mode is available that allows the clock that is input through the OMCK pin to b

26 DS586F2CS42528When either serial port is in Slave Mode, its respective LRCK signal must be present for proper deviceoperation.In Slave Mode, One-Li

DS586F2 27CS42528 Serial Inputs / OutputsCX_SDIN1 left channel right channel

28 DS586F2CS425284.6.2 Serial Audio Interface FormatsThe CODEC_SP and SAI_SP digital audio serial ports support five formats with varying bit depths f

DS586F2 29CS42528CX_LRCKSAI_LRCKCX_SCLKSAI_SCLKLeft ChannelRight ChannelCX_SDINxCX_SDOUTSAI_SDOUT+3 +2 +1+5 +4-1 -2 -3 -4 -5+3 +2 +1+5 +4-1-2 -3 -4MSB

DS586F2 3CS425286. REGISTER DESCRIPTION ...

30 DS586F2CS42528Figure 13. One-Line Mode #1 Serial Audio FormatOne-Line Data Mode #1, Data Valid on Rising Edge of SCLKBits/SampleSCLK Rate(s)NotesM

DS586F2 31CS425284.6.3 ADCIN1/ADCIN2 Serial Data FormatThe two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, sup

32 DS586F2CS425284.6.4 One-Line Mode (OLM) Configurations4.6.4.1 OLM Config #1One-Line Mode Configuration #1 can support up to 8 channels of DAC data,

DS586F2 33CS425284.6.4.2 OLM Config #2This configuration will support up to 8 channels of DAC data or 6 channels of ADC data and no channelsof S/PDIF

34 DS586F2CS425284.6.4.3 OLM Config #3This One Line Mode configuration #3 will support up to 8 channels of DAC data, 6 channels of ADC data and 2 chan

DS586F2 35CS425284.6.4.4 OLM Config #4This configuration will support up to 8 channels of DAC data 6 channels of ADC data and no channels ofS/PDIF rec

36 DS586F2CS425284.6.4.5 OLM Config #5This One-Line Mode configuration can support up to 8 channels of DAC data 2 channels of ADC data and2 channels o

DS586F2 37CS425284.7 Control Port Description and TimingThe control port is used to access the registers, allowing the CS42528 to be configured for th

38 DS586F2CS425284.7.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

DS586F2 39CS42528Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected r

4 DS586F2CS4252810.1.4 Circuit Board Layout ...

40 DS586F2CS42528For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog+5 V supply for VARX, deco

DS586F2 41CS425285. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 001hIDChip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0page

42 DS586F2CS425280FhVol. Control A1A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0page 58default0 0 00000 010hVol. Control B1B1_VOL7 B

DS586F2 43CS425281EhRCVR Mode Ctrl SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 HOLD1 HOLD0page 61default0 0 00000 01FhRCVR Mode Ctrl 2Reserved TMUX2

44 DS586F2CS425282DhRXP3/GPO3Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0page 69default0 0 00000 02EhRXP2/GPO2Mode1 Mode0 Po

DS586F2 45CS425286. REGISTER DESCRIPTIONAll registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Interrupt

46 DS586F2CS425286.3 Power Control (address 02h)6.3.1 POWER DOWN RECEIVER (PDN_RCVRX)Default = 1000 - Receiver and PLL in normal operational mode.01 -

DS586F2 47CS425286.4 Functional Mode (address 03h)6.4.1 CODEC FUNCTIONAL MODE (CODEC_FMX)Default = 0000 - Single-Speed Mode (4 to 50 kHz sample rates)

48 DS586F2CS42528Receiver Mode Control (address 1Eh) register to set the appropriate sample rate. 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM)Defaul

DS586F2 49CS425286.5 Interface Formats (address 04h)6.5.1 DIGITAL INTERFACE FORMAT (DIFX)Default = 01Function:These bits select the digital interface

DS586F2 5CS42528Figure 42. Quad-Speed Mode Stopband Rejection ...84Fig

50 DS586F2CS425286.5.4 SAI RIGHT-JUSTIFIED BITS (SAI_RJ16)Default = 0Function:This bit determines how many bits to use during right-justified mode for

DS586F2 51CS425286.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)Default = 0Function:This feature allows the user to select whether the DAC interpolation

52 DS586F2CS425286.7 Clock Control (address 06h)6.7.1 RMCK DIVIDE (RMCK_DIVX)Default = 00Function:Divides/multiplies the internal MCLK, either from th

DS586F2 53CS425286.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)Default = 00Function:These two bits, along with the UNLOCK bit in register “Interrupt Stat

54 DS586F2CS425286.9 RVCR Status (address 08h) (Read Only)6.9.1 DIGITAL SILENCE DETECTION (DIGITAL SILENCE)Default = x0 - Digital Silence not detected

DS586F2 55CS425286.9.4 RECEIVER CLOCK FREQUENCY (RCVR_CLKX)Default = xxxFunction:The CS42528 detects the ratio between the OMCK and the recovered cloc

56 DS586F2CS425286.11 Volume Transition Control (address 0Dh)6.11.1 SINGLE VOLUME CONTROL (SNGVOL)Default = 0Function:The individual channel volume le

DS586F2 57CS425286.11.3 AUTO-MUTE (AMUTE)Default = 10 - Disabled1 - EnabledFunction:The digital-to-analog converters of the CS42528 will mute the out

58 DS586F2CS425286.12 Channel Mute (address 0Eh)6.12.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)Default = 00 - Disabled1 - EnabledFunction:The digital-to-ana

DS586F2 59CS42528Mixing Control Pair 2 (Channels A2 & B2) (address 19h)Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah)Mixing Control Pa

6 DS586F2CS425281. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Cond

60 DS586F2CS425286.15.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001Function:The CS42528 implements the channel-mixing functions of the

DS586F2 61CS425286.16 ADC Left Channel Gain (address 1Ch)6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)Default = 00hFunction:The level of the left analog chann

62 DS586F2CS425286.18.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)Default = 0000 - Reserved01 - De-Emphasis for 32 kHz sample rate.10 - De-Emphasis for 44.1 k

DS586F2 63CS425286.19 Receiver Mode Control 2 (address 1Fh)6.19.1 TXP MULTIPLEXER (TMUXX)Default = 000Function:Selects which of the eight receiver inp

64 DS586F2CS425286.20.1 PLL UNLOCK (UNLOCK)Default = 0Function:PLL unlock status bit. This bit will go high if the PLL becomes unlocked.6.20.2 NEW Q-S

DS586F2 65CS425286.22 Interrupt Mode MSB (address 22h)Interrupt Mode LSB (address 23h)Default = 00000000Function:The two Interrupt Mode registers form

66 DS586F2CS425286.23.3 C-DATA BUFFER CONTROL (CAM)Default = 00 - One byte mode1 - Two byte modeFunction:Sets the C-data buffer control port access mo

DS586F2 67CS425286.24.2 CHANNEL STATUS BLOCK FORMAT (PRO)Default = xFunction:Indicates the channel status block format.6.24.3 AUDIO INDICATOR (AUDIO)D

68 DS586F2CS425286.25.3 PLL LOCK STATUS (UNLOCK)Default = x0 - PLL locked1 - PLL out of lockFunction:Indicates the lock status of the PLL.6.25.4 RECEI

DS586F2 69CS42528the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiv

DS586F2 7CS42528ANALOG INPUT CHARACTERISTICS(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Mea-sur

70 DS586F2CS42528or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the left or right ch

DS586F2 71CS42528following table. It is recommended that in this mode the remaining functional bits be set to 0.GPO, Drive High - If the pin is config

72 DS586F2CS425287. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS586F2 73CS425288. APPENDIX A: EXTERNAL FILTERS8.1 ADC Input FilterThe analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). Th

74 DS586F2CS425289. APPENDIX B: S/PDIF RECEIVER9.1 Error Reporting and Hold FunctionThe UNLOCK bit indicates whether the PLL is locked to the incoming

DS586F2 75CS425289.2.1 Channel Status Data E Buffer AccessThe user can monitor the incoming Channel Status data by reading the E buffer, which is mapp

76 DS586F2CS425289.2.2 Serial Copy Management System (SCMS)The CS42528 allows read access to all the channel status bits. For consumer mode SCMS compl

DS586F2 77CS4252810.APPENDIX C: PLL FILTERThe PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information

78 DS586F2CS42528The external PLL component values listed in Table 21 have a high corner-frequency jitter-attenuationcurve, take a short time to lock,

DS586F2 79CS4252810.1.2 Jitter AttenuationFigures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range whenused

8 DS586F2CS42528A/D DIGITAL FILTER CHARACTERISTICS Notes:5. The filter frequency response scales precisely with Fs.6. Response shown is for Fs equal

80 DS586F2CS4252810.1.3 Capacitor SelectionThe type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large

DS586F2 81CS4252810.1.4 Circuit Board LayoutBoard layout and capacitor choice affect each other and determine the performance of the PLL. Figure30 ill

82 DS586F2CS4252811.APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS 11.1 AES3 Receiver External ComponentsThe CS42528 AES3 receiver is d

DS586F2 83CS4252812.APPENDIX E: ADC FILTER PLOTS -140-130-120-110-100-90-80-70-60-50-40-30-20-1000.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Frequency

84 DS586F2CS42528 -10-9-8-7-6-5-4-3-2-100.40 0.43 0.45 0.48 0.50 0.53 0.55Frequency (normalized to Fs)Amplitude (dB) -0.10-0.08-0.05-0.030.

DS586F2 85CS4252813.APPENDIX F: DAC FILTER PLOTS0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.4 0.42 0.44 0.46 0.

86 DS586F2CS425280 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.020.0150.010.00500.0050.010.0150.02Frequency(normalized to Fs)Amplitude (dB)0.45 0.46

DS586F2 87CS425280.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.8120100806040200Fr

88 DS586F2CS425280.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.250.2

DS586F2 89CS4252814.PACKAGE DIMENSIONS THERMAL CHARACTERISTICSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.

DS586F2 9CS42528ANALOG OUTPUT CHARACTERISTICS(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measure

90 DS586F2CS4252815.ORDERING INFORMATION16.REFERENCES1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.http://www.cirrus.com

DS586F2 91CS4252817.REVISION HISTORY Release Date ChangesF1 October 2005Final Release– Added ordering information table on page 90.– Updated registers

92 DS586F2CS42528