Cirrus-logic CS4245 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com104 dB, 24-Bit, 192 kHz Stereo Audio CODECD/A Features Multi-bit Delta S

10 DS656F3CS4245DAC ANALOG CHARACTERISTICSTest Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25

DS656F3 11CS42456. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance andmaximum capacitance required for the in

12 DS656F3CS4245 AOUTxAGND3.3µFVoutRLCLFigure 1. DAC Output Test Load Figure 2. Maximum DAC Loading1005075252.551015Safe OperatingRegionCapaci

DS656F3 13CS4245ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25

14 DS656F3CS424511. Valid for the selected input pair.DC AccuracyGain Error --10 %Gain Drift - 100 - ppm/°CLine-Level Input CharacteristicsFull-scal

DS656F3 15CS4245ADC ANALOG CHARACTERISTICS (Continued) 12. Referred to the typical line-level full-scale input voltage13. Valid for Double- and Qu

16 DS656F3CS4245ADC DIGITAL FILTER CHARACTERISTICS 15. Filter response is guaranteed by design.16. Response shown is for Fs = 48 kHz. 17. Resp

DS656F3 17CS4245AUXILIARY OUTPUT ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3

18 DS656F3CS4245AUXILIARY OUTPUT ANALOG CHARACTERISTICS (Continued)18. One-half LSB of triangular PDF dither added to data.19. Referred to the typical

DS656F3 19CS424520. Referred to the typical DAC Full-Scale Output Voltage.AUXILIARY OUTPUT ANALOG CHARACTERISTICS (Continued) 21. Valid only when PGA

2 DS656F3CS4245System Features Direct Interface with 1.8 V to 5 V Logic Levels Optional Asynchronous Serial Port Operation– Each Serial Port Support

20 DS656F3CS4245DC ELECTRICAL CHARACTERISTICSAGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.23. Power

DS656F3 21CS4245DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.26. Ser

22 DS656F3CS4245SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 28)28. See Figure 3 a

DS656F3 23CS4245 slrtSDOUTSCLK1OutputLRCK1OutputsdotslrtSDOUTSCLK1InputLRCK1InputsdotsclkhtsclkltsclkwtFigure 3. Master Mode Timing -

24 DS656F3CS4245SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 29) 29. See Figure 5 a

DS656F3 25CS4245 sdistslrtSCLK2OutputLRCK2OutputSDINsdihtsdistslrtSCLK2InputLRCK2InputSDINsdihtsclkhtsclkltsclkwtFigure 5. Master Mod

26 DS656F3CS4245 Figure 7. Format 0, Left-Justified up to 24-Bit DataLRCKSCLK SDATA+3 +2 +1+5 +4-1 -2 -3 -4 -5+3 +2 +1+5 +4MSB-1 -2 -3 -4Channel A -

DS656F3 27CS4245SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMATInputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.30. Data must be held

28 DS656F3CS4245SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.32. Data must be hel

DS656F3 29CS42453. TYPICAL CONNECTION DIAGRAMVLS0.1 µF+1.8Vto +5VMUTECMuteDriveDGNDVLC0.1 µF+1.8Vto +5VSCL/CCLKSDA/CDOUTAD1/CDINRESET2 kSee Note 1LRC

DS656F3 3CS4245TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS656F3CS42454. APPLICATIONS4.1 Recommended Power-Up Sequence1. Hold RESET low until the power supply, MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are

DS656F3 31CS4245in Master Mode, and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required

32 DS656F3CS42454.2.3 Master ModeAs a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently placed into Maste

DS656F3 33CS4245The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimationfilter. If the HPFFreeze bit (

34 DS656F3CS42454.4 Analog Input Multiplexer, PGA, and Mic GainThe CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable

DS656F3 35CS42454.7 Output Transient ControlThe CS4245 uses Popguard® technology to minimize the effects of output transients during power-up andpower

36 DS656F3CS4245De-emphasis is only available in Single-Speed Mode. 4.10 Internal Digital LoopbackThe CS4245 supports an internal digital loopback

DS656F3 37CS4245signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.The MUTEC pin is an ac

38 DS656F3CS4245dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT wil

DS656F3 39CS4245Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 19, the write operat

4 DS656F3CS42456.2.4 Power-Down DAC (Bit 1) ... 43

40 DS656F3CS42454.14 ResetWhen RESET is low, the CS4245 enters a low-power mode and all internal states are reset, including thecontrol port and regis

DS656F3 41CS42455. REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5 4 3 2 1 001h Ch

42 DS656F3CS42456. REGISTER DESCRIPTION6.1 Chip ID - Register 01hFunction:This register is Read-Only. Bits 7 through 4 are the part number ID, which i

DS656F3 43CS42456.2.4 Power-Down DAC (Bit 1)Function:The DAC pair will remain in a reset state whenever this bit is set.6.2.5 Power-Down Device (Bit 0

44 DS656F3CS42456.3.4 De-Emphasis Control (Bit 1)Function:The standard 50/15 s digital de-emphasis filter response, Figure 20, may be implemented for

DS656F3 45CS42456.4.2 ADC Digital Interface Format (Bit 4)Function:The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digi

46 DS656F3CS42456.5.2 Master Clock 2 Frequency (Bits 2:0)Function:These bits set the frequency of the supplied MCLK2 signal. See Table 13 for the appr

DS656F3 47CS42456.7 Channel B PGA Control - Address 07h6.7.1 Channel B PGA Gain (Bits 5:0)Function:See “Channel A PGA Gain (Bits 5:0)” on page 47.6.8

48 DS656F3CS4245occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-ple rate) if the signal does not e

DS656F3 49CS4245shown in Table 18. The volume changes are implemented as dictated by the DACSoft and DACZero-Cross bits in the DAC Control 2 register

DS656F3 5CS4245LIST OF FIGURESFigure 1.DAC Output Test Load ...

50 DS656F3CS42456.12.3 Active High/Low (Bit 0)Function:When this bit is set, the INT pin functions as an active high CMOS driver. When this bit is cle

DS656F3 51CS42456.15 Interrupt Mode MSB - Address 0Fh6.16 Interrupt Mode LSB - Address 10hFunction:The two Interrupt Mode registers form a 2-bit code

52 DS656F3CS42457. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

DS656F3 53CS42458. DAC FILTER PLOTS Figure 21. DAC Single-Speed Stopband Rejection Figure 22. DAC Single-Speed Transition Band0 0.05 0.1 0.15

54 DS656F3CS4245 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-0. 2-0. 100.10.20.30.40.50.60.70.8Frequency (normalized to Fs)Amplitud

DS656F3 55CS42459. ADC FILTER PLOTS Figure 33. ADC Single-Speed Stopband Rejection Figure 34. ADC Single-Speed Stopband RejectionFigure 35. AD

56 DS656F3CS4245 Figure 39. ADC Double-Speed Transition Band (Detail) Figure 40. ADC Double-Speed Passband RippleFigure 41. ADC Qua

DS656F3 57CS424510.PACKAGE DIMENSIONS11.THERMAL CHARACTERISTICS AND SPECIFICATIONS 1. JA is specified according to JEDEC specifications for multi-la

58 DS656F3CS424512.ORDERING INFORMATION 13.REVISION HISTORYProduct Description Package Pb-Free Grade Temp Range Container Order #CS424524-bit,

DS656F3 59CS4245Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one n

6 DS656F3CS4245Table 6. Freeze-able Bits ...

DS656F3 7CS42451. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDA/CDOUT 1Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDOUT

8 DS656F3CS4245AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.VA 14 Analog Power (Input) - Positive power for the in

DS656F3 9CS42452. CHARACTERISTICS AND SPECIFICATIONSSPECIFIED OPERATING CONDITIONSAGND = DGND = 0 V; All voltages with respect to ground.Notes: 1. Max