Cirrus-logic CS4244 Instrukcja Użytkownika Strona 29
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DS900F1 29
CS4244
SDIN1
Input Data
1.1
[31:8]
x
[7:0]
Input Data
1.2
[31:8]
x
[7:0]
Input Data
1.3
[31:8]
x
[7:0]
Input Data
1.4
[31:8]
x
[7:0]
Input Data
1.5
[31:8]
x
[7:0]
Input Data
1.6
[31:8]
x
[7:0]
Input Data
1.7
[31:8]
x
[7:0]
Input Data
1.8
[31:8]
x
[7:0]
SDIN2
Input Data
2.1
[31:8]
x
[7:0]
Input Data
2.2
[31:8]
x
[7:0]
Input Data
2.3
[31:8]
x[7:0]
Input Data
2.4
[31:8]
x
[7:0]
Input Data
2.5
[31:8]
x
[7:0]
Input Data
2.6
[31:8]
x[7:0]
Input Data
2.7
[31:8]
x[7:0]
Input Data
2.8
[31:8]
x[7:0]
SDOUT1
ADC1
Data[31:8]
0's
[7:0]
ADC2 Data
[31:8]
0's
[7:0]
ADC3 Data
[31:8]
0's
[7:0]
ADC4
Data[31:8]
0's
[7:0]
SDOUT1
with
Sidechain
ADC1
Data[31:8]
0's
[7:0]
ADC2 Data
[31:8]
0's
[7:0]
ADC3 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
MCLK = 12.288/24.576MHz
FS/LRCK = 48/96kHz
SCLK = 12.288/24.576MHz
Slot 1 [31:0] Slot 2 [31:0] Slot 3 [31:0] Slot 4 [31:0] Slot 5 [31:0] Slot 6 [31:0] Slot 7 [31:0] Slot 8 [31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
Output Data
(SDIN2 Slot 1)
Output Data
(SDIN2 Slot 2)
Output Data
(SDIN2 Slot 3)
Output Data
(SDIN2 Slot 4)
SDIN1
Input Data
1.1
[31:8]
x
[7:0]
Input Data
1.4
[31:8]
x
[7:0]
Input Data
1.5
[31:8]
x
[7:0]
Input Data
1.8
[31:8]
x
[7:0]
Input Data
1.9
[31:8]
x
[7:0]
Input Data
1.12
[31:8]
x
[7:0]
Input Data
1.13
[31:8]
x
[7:0]
Input Data
1.16
[31:8]
x
[7:0]
SDIN2
Input Data
2.1
[31:8]
x
[7:0]
Input Data
2.4
[31:8]
x
[7:0]
Input Data
2.5
[31:8]
x
[7:0]
Input Data
2.8
[31:8]
x
[7:0]
Input Data
2.9
[31:8]
x
[7:0]
Input Data
2.12
[31:8]
x
[7:0]
Input Data
2.13
[31:8]
x
[7:0]
Input Data
2.16
[31:8]
x
[7:0]
SDOUT1
ADC1 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
SDOUT1
with
Sidechain
ADC1 Data
[31:8]
0's
[7:0]
ADC4 Data
[31:8]
0's
[7:0]
MCLK = 24.576MHz
FS/LRCK = 48kHz
0's
[31:0]
Output Data
(SDIN2 Slot 1)
SCLK = 24.576MHz
Slot 1 [31:0]
…→…
Slot 4 [31:0] Slot 5 [31:0]
…→…
Slot 8 [31:0] Slot 9 [31:0] Slot 13 [31:0]
…→…
Slot 16 [31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
0's
[31:0]
…→…
Slot 12 [31:0]
Output Data
(SDIN2 Slot 12)
Output Data
(SDIN2 Slot 4)
Output Data
(SDIN2 Slot 5)
Output Data
(SDIN2 Slot 8)
Output Data
(SDIN2 Slot 9)
Figure 16. Serial Data Coding and Extraction Options within the TDM Streams
- DAC Features 1
- ADC Features 1
- System Features 1
- Common Applications 1
- General Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 4
- 1. PIN DESCRIPTIONS 5
- 1.1 I/O Pin Characteristics 6
- Digital Signal 7
- Processor 7
- ABSOLUTE MAXIMUM RATINGS 8
- TYPICAL CURRENT CONSUMPTION 10
- (Note 13) 11
- CS4244 AINx 13
- DS900F1 13 13
- CS4244 AINx + 13
- 25000/Fs 14
- DIGITAL I/O CHARACTERISTICS 18
- DS900F1 20 20
- 4. APPLICATIONS 22
- 4.2.2 Power-down 23
- 4.2.3 DAC DC Loading 23
- 4.3 I²C Control Port 24
- CS4244 after 25
- CS4244, the chip address 25
- 4.3.1.1 Map Increment (INCR) 26
- 4.4 System Clocking 26
- 4.4.1 Master Clock 26
- 4.4.3 Slave Mode Clock Ratios 27
- 4.5 Serial Port Interface 28
- 4.5.1 TDM Mode 28
- DS900F1 29 29
- 4.6 Internal Signal Path 31
- 4.6.1.1 ADC Signal Routing 31
- 4.6.1.2 DAC1-4 Signal Routing 32
- 4.6.2 ADC Path 35
- 4.6.2.1 Analog Inputs 35
- 4.6.2.3 ADC HPF 36
- 4.6.3 DAC1-4 Path 37
- 4.6.3.1 De-emphasis Filter 37
- 4.6.4 Analog Outputs 38
- 4.6.5 Volume Control 39
- 4.6.5.1 Mute Behavior 39
- 4.6.5.2 Soft Ramp 39
- MIN_DELAY 40
- MAX_DELAY 40
- 4.6.5.3 Noise Gate 41
- 4.7 Reset Line 42
- 4.8.1 Interrupt Masking 43
- DS900F1 44 44
- 5. REGISTER QUICK REFERENCE 45
- DS900F1 46 46
- 6. REGISTER DESCRIPTIONS 47
- 6.3.1 Base Rate Advisory 48
- 6.3.2 Speed Mode 48
- 6.3.3 Master Clock Rate 48
- 76543210 49
- 6.5.4 Master/Slave 50
- 6.6.1 DAC1-4 Data Source 50
- 6.9.1 DAC1-4 Noise Gate 52
- 6.9.2 DAC1-4 De-emphasis 52
- 6.10.1 Inv. DACx 52
- 6.13.1 Mute Delay 54
- 6.13.2 Minimum Delay 54
- 6.13.3 Maximum Delay 54
- 6.14.1 x Volume Control 55
- 6.15.1 INT MODE 55
- Reserved 57
- 6.19.1 DACx Clip 58
- 7. ADC FILTER PLOTS 59
- 8. DAC FILTER PLOTS 60
- DS900F1 61 61
- 9. PACKAGE DIMENSIONS 62
- 10.ORDERING INFORMATION 63
- 11.REVISION HISTORY 63
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