Cirrus-logic CS2000-OTP Instrukcja Użytkownika Pobierz pdf

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Fractional-N Clock Synthesizer & Clock Multiplier

Features

 Delta-Sigma Fractional-N Frequency Synthesis

– Generates a Low Jitter 6 - 75 MHz Clock

from an 8 - 75 MHz Reference Clock

 Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery 50 Hz to 30 MHz Clock

Source

 Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM in High-

Resolution Mode

 One-Time Programmability

– Configurable Hardware Control Pins

– Configurable Auxiliary Output

 Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source

– Supports Inexpensive Local Crystal

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2000-OTP is an extremely versatile system

clocking device that utilizes a programmable phase lock

loop. The CS2000-OTP is based on a hybrid analog-

digital PLL architecture comprised of a unique combina-

tion of a Delta-Sigma Fractional-N Frequency

Synthesizer and a Digital PLL. This architecture allows

for both frequency synthesis/clock generation from a

stable reference clock as well as generation of a low-jit-

ter clock relative to an external noisy synchronization

clock with frequencies as low as 50 Hz. The CS2000-

OTP has many configuration options which are set once

prior to runtime. At runtime there are three hardware

configuration pins available for mode and feature

selection.

The CS2000-OTP is available in a 10-pin MSOP pack-

age in Commercial (-10°C to +70°C) and Automotive

(-40°C to +85°C) grades. Customer development kits

are also available for custom device prototyping, small

production programming, and device evaluation.

Please see “Ordering Information” on page 29 for com-

plete details.

Hardware Configuration

Auxiliary

Output

6 to 75 MHz

PLL Output

Frequency Reference

3.3 V

Hardware Control

8 MHz to 75 MHz

Low-Jitter Timing Reference

Fractional-N

Frequency Synthesizer

Digital PLL & Fractional

N Logic

Output to Input

Clock Ratio

Timing Reference

PLL Output

Lock Indicator

50 Hz to 30 MHz

Frequency Reference

Output to Input

Clock Ratio

MAY '10

DS758F2

CS2000-OTP

1 2 3 4 5 6 ... 29 30

Podsumowanie treści

Strona 1 - CS2000-OTP

Strona 2

CS2000-OTP10 DS758F2 Figure 6. Hybrid Analog-Digital PLL4.2.1 Fractional-N Source Selection for the Frequency SynthesizerThe fractional-N value for t

Strona 3

CS2000-OTPDS758F2 115. APPLICATIONS5.1 One Time ProgrammabilityThe one time programmable (OTP) circuitry in the CS2000-OTP allows for pre-configuratio

Strona 4 - 1. PIN DESCRIPTION

CS2000-OTP12 DS758F2example of how to determine the range of RefClk frequencies around 12 MHz to be used in order toachieve the lowest jitter PLL outp

Strona 5 - 2. TYPICAL CONNECTION DIAGRAM

CS2000-OTPDS758F2 13which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency referenceclock through the Digital P

Strona 6 - DC ELECTRICAL CHARACTERISTICS

CS2000-OTP14 DS758F2While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock isachieved, the digital loop ban

Strona 7 - AC ELECTRICAL CHARACTERISTICS

CS2000-OTPDS758F2 155.4.3 Ratio Modifier (R-Mod)The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio0-3 stored

Strona 8 - PLL PERFORMANCE PLOTS

CS2000-OTP16 DS758F25.4.5.1 Manual Fractional-N Source Selection for the Frequency SynthesizerManual selection of the fractional-N source for the freq

Strona 9 - 4. ARCHITECTURE OVERVIEW

CS2000-OTPDS758F2 175.4.6 Ratio Configuration SummaryThe RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored

Strona 10

CS2000-OTP18 DS758F25.5 PLL Clock OutputThe PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.The

Strona 11 - 5. APPLICATIONS

CS2000-OTPDS758F2 195.7 Mode Pin Functionality5.7.1 M1 and M0 Mode Pin FunctionalityM[1:0] determine the functional mode of the device and select both

Strona 12

CS2000-OTPDS758F2 2TABLE OF CONTENTS1. PIN DESCRIPTION ...

Strona 13

CS2000-OTP20 DS758F25.7.2.3 M2 Configured as Auto Fractional-N Source Selection DisableIf M2Config[2:0] is set to ‘100’, M2 becomes a disable pin for

Strona 14

CS2000-OTPDS758F2 215.8.2 PLL Unlock ConditionsCertain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect thep

Strona 15

CS2000-OTP22 DS758F26. PARAMETER DESCRIPTIONSAs mentioned in Section 5.1 on page 11, there are two different kinds of parameter configuration sets, Mo

Strona 16

CS2000-OTPDS758F2 236.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])Selects the source of the AUX_OUT signal.Note: When set to 11, the AuxLock

Strona 17

CS2000-OTP24 DS758F26.3 Global Configuration Parameters6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg)When the AUX_OUT pin is configured as a loc

Strona 18

CS2000-OTPDS758F2 256.3.5 M2 Pin Configuration (M2Config[2:0])Controls which special function is mapped to the M2 pin.6.3.6 Clock Input Bandwidth (Clk

Strona 19

CS2000-OTP26 DS758F27. CALCULATING THE USER DEFINED RATIONote: The software for use with the evaluation kit has built in tools to aid in calculating a

Strona 20

CS2000-OTPDS758F2 278. PROGRAMMING INFORMATIONField programming of the CS2000-OTP is achieved using the hardware and software tools included with theC

Strona 21

CS2000-OTP28 DS758F29. PACKAGE DIMENSIONSNotes: 1. Reference document: JEDEC MO-1872. D does not include mold flash or protrusions which is 0.15 mm ma

Strona 22 - 6. PARAMETER DESCRIPTIONS

CS2000-OTPDS758F2 2910.ORDERING INFORMATIONThe CS2000-OTP is ordered as an un-programmed device. The CS2000-OTP can also be factory programmed forlarg

Strona 23

CS2000-OTPDS758F2 36.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) ... 246.3.3

Strona 24

CS2000-OTP30 DS758F2Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one n

Strona 25

CS2000-OTP4 DS758F21. PIN DESCRIPTIONPin Name # Pin DescriptionVD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.

Strona 26

CS2000-OTPDS758F2 52. TYPICAL CONNECTION DIAGRAM 21GNDM2M1XTI/REF_CLKFrequency Reference CLK_INXTOCLK_OUTAUX_OUT0.1 µFVD+3.3 VM0Low-JitterTiming Ref

Strona 27 - 8. PROGRAMMING INFORMATION

CS2000-OTP6 DS758F23. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 1)Notes

Strona 28 - THERMAL CHARACTERISTICS

CS2000-OTPDS758F2 7AC ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Gra

Strona 29 - 11.REVISION HISTORY

CS2000-OTP8 DS758F2PLL PERFORMANCE PLOTSTest Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; fCLK_OUT= 12.288 MHz; fCLK_IN= 12.

Strona 30

CS2000-OTPDS758F2 94. ARCHITECTURE OVERVIEW4.1 Delta-Sigma Fractional-N Frequency SynthesizerThe core of the CS2000 is a Delta-Sigma Fractional-N Freq

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