Cirrus-logic AN312 Instrukcja Użytkownika Pobierz pdf (Strona 8)

8 AN312REV2

AN312

Figure 13. Clock Circuit as Used by Mode 0x04 with CM-1 Module

Figure 14. Clock Circuit as Used by Mode 0x04 with CM-2 and Semiconductors

Beat Received

VCXO

24.576MHz

+/- 100 PPM

DAC

MCLK_IN

MCLK_SEL

REFCLK_Enable

REFCLK_Polarity

REFCLK

Edge

Detect

MCLK

MUX

Beat

MUX

Phase

Detector

Sample

Phase

Counter

RST

Loop

Filter

control

Clock

Out

MCLK_OUT (master)

FS1 (word)

SCK (bit)

Audio

Clock

Generator

Clock Config

Signal

Path

Control

Path

Hardware FPGA Software

Active

Signal

Path

Beat Received

VCXO

24.576MHz

+/- 100 PPM

DAC

MCLK_IN

MCLK_SEL

REFCLK

MCLK

MUX

Beat

MUX

Phase

Detector

Sample

Phase

Counter

Loop

Filter

control

Clock

Out

MCLK_OUT (master)

FS1 (word)

SCK (bit)

Audio

Clock

Generator

Clock Config

Signal

Path

Control

Path

External

Hardware

CobraNet

Processor

Software

Active

Signal

Path

1 2 3 4 5 6 7 8 9 10 11 12 13 14

CobraNet 1
Clocking Modes 1
2 AN312REV2 2
3.1 CobraNet Clock Modes 3
6 AN312REV2 6
8 AN312REV2 8
3.1.5.1 0x14 Mode for CM-1 9
10 AN312REV2 10
5. REFERENCES 12
6. REVISION HISTORY 13
14 AN312REV2 14

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Cirrus-logic AN312 Instrukcja Użytkownika Strona 8

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