Cirrus-logic CS2000-CP Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comFractional-N Clock Synthesizer & Clock MultiplierFeatures Delta-Sigm

CS2000-CP10 DS761F2CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMATInputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 12. Data must be held for suf

CS2000-CPDS761F2 11CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.Notes: 13.tspi is only needed befo

CS2000-CP12 DS761F24. ARCHITECTURE OVERVIEW4.1 Delta-Sigma Fractional-N Frequency SynthesizerThe core of the CS2000 is a Delta-Sigma Fractional-N Freq

CS2000-CPDS761F2 13 Figure 8. Hybrid Analog-Digital PLL4.2.1 Fractional-N Source Selection for the Frequency SynthesizerThe fractional-N value for th

CS2000-CP14 DS761F25. APPLICATIONS5.1 Timing Reference Clock InputThe low jitter timing reference clock (RefClk) can be provided by either an external

CS2000-CPDS761F2 155.1.2 Crystal Connections (XTI and XTO)An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental

CS2000-CP16 DS761F2Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 SysClk cycles (466 msto 1048 ms) after CLK_IN i

CS2000-CPDS761F2 17If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn bit determines whether PLL_OUTcontinues while the PLL re-acquire

CS2000-CP18 DS761F2Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-tem clocks and associated d

CS2000-CPDS761F2 195.3 Output to Input Frequency Ratio Configuration5.3.1 User Defined Ratio (RUD), Frequency Synthesizer ModeThe User Defined Ratio,

CS2000-CP2 DS761F2TABLE OF CONTENTS1. PIN DESCRIPTION ...

CS2000-CP20 DS761F25.3.3 Ratio Modifier (R-Mod)The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (the Ratio0-3 stor

CS2000-CPDS761F2 215.3.5 Fractional-N Source SelectionTo select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based

CS2000-CP22 DS761F25.3.6 Ratio Configuration SummaryThe RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored i

CS2000-CPDS761F2 235.4 PLL Clock OutputThe PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.The d

CS2000-CP24 DS761F25.6 Clock Output Stability Considerations5.6.1 Output SwitchingCS2000 is designed such that re-configuration of the clock routing f

CS2000-CPDS761F2 25The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Modeis selected if th

CS2000-CP26 DS761F2Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 22, the write oper

CS2000-CPDS761F2 276.3 Memory Address PointerThe Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be reador

CS2000-CP28 DS761F28. REGISTER DESCRIPTIONSIn I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only.

CS2000-CPDS761F2 298.2.3 PLL Clock Output Disable (ClkOutDis)This bit controls the output driver for the CLK_OUT pin. 8.3 Device Configuration 1 (Add

CS2000-CPDS761F2 38.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ... 298.3.4 Enabl

CS2000-CP30 DS761F28.3.4 Enable Device Configuration Registers 1 (EnDevCfg1)This bit, in conjunction with EnDevCfg2, configures the device for control

CS2000-CPDS761F2 318.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) This bit, in conjunction with EnDevCfg1, configures the device for contro

CS2000-CP32 DS761F28.7.2 AUX PLL Lock Output Configuration (AuxLockCfg)When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), t

CS2000-CPDS761F2 338.9 Function Configuration 3 (Address 1Eh)8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0])Sets the minimum loop bandwidth when locked to

CS2000-CP34 DS761F29. CALCULATING THE USER DEFINED RATIONote: The software for use with the evaluation kit has built in tools to aid in calculating an

CS2000-CPDS761F2 3510.PACKAGE DIMENSIONSNotes: 1. Reference document: JEDEC MO-1872. D does not include mold flash or protrusions which is 0.15 mm max

CS2000-CP36 DS761F211.ORDERING INFORMATION12.REFERENCES1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measure

CS2000-CPDS761F2 37

CS2000-CP38 DS761F2Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one ne

CS2000-CP4 DS761F2LIST OF TABLESTable 1. Ratio Modifier ...

CS2000-CPDS761F2 51. PIN DESCRIPTIONPin Name # Pin DescriptionVD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.G

CS2000-CP6 DS761F22. TYPICAL CONNECTION DIAGRAM 21GNDSCL/CCLKSDA/CDIN2 kΩXTI/REF_CLKFrequency Reference CLK_INXTOCLK_OUTAUX_OUT0.1 µFVD+3.3 VNotes:1.

CS2000-CPDS761F2 73. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 1)Notes:

CS2000-CP8 DS761F2AC ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grad

CS2000-CPDS761F2 9PLL PERFORMANCE PLOTSTest Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; fCLK_OUT= 12.288 MHz; fCLK_IN= 12.2