Cirrus-logic CS4228A Instrukcja Użytkownika Pobierz pdf (Strona 23)

CS4228A

DACPDN12 Power down the analog section of DAC 1 and 2

*0 - Normal

1 - Power down DAC 1 and 2.

DACPDN34 Power down the analog section of DAC 3 and 4

*0 - Normal

1 - Power down DAC 3 and 4.

DACPDN56 Power down the analog section of DAC 5 and 6

*0 - Normal

1 - Power down DAC 5 and 6.

5.4 ADC Control

Address 0x03

MUTL, MUTR ADC left and right channel mute control

*0 - Normal

1 - Selected ADC output muted

HPF ADC DC offset removal. See “High Pass Filter” for more information

*0 - Enabled

1 - Disabled

HPFZ ADC DC offset averaging freeze. See “High Pass Filter” for more information

*0 - Normal. The DC offset average is dynamically calculated and subtracted from in-

coming

ADC data.

1 - Freeze. The DC offset average is frozen at the current value and subtracted from

incoming ADC data. Allows passthru of DC information.

5.5 DAC Mute1 Control

Address 0x04

MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally

attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu-

ation value returns to the value stored in the corresponding Digital Volume Control register. The

attenuation value is ramped up and down at the rate specified by RMP1:0.

0 - Normal output level

*1 - Selected DAC output fully attenuated.

RMP1:0 Attenuation ramp rate.

*0 - 0.5 dB change per 4 LRCKs

1- 0.5dBchangeper8LRCKs

2 - 0.5 dB change per 16 LRCKs

3 - 0.5 dB change per 32 LRCKs

76543210

MUTL MUTR HPF HPFZ RESERVED

00000000

76543210

MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 RMP1 RMP0

11111100

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 31 32

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