Cirrus-logic CS4228A Instrukcja Użytkownika Pobierz pdf (Strona 10)

CS4228A

SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)

Notes: 18. Data must be held for sufficient time to bridge the transition time of CCLK.

19. For F

SCK

<1MHz

Parameter Symbol Min Max Units

SPI Mode (SDOUT > 47 kΩ to GND)

CCLK Clock Frequency f

sck

-6MHz

High Time Between Transmissions t

csh

1.0 µs

Falling to CCLK Edge t

css

20 ns

CCLK Low Time t

scl

66 ns

CCLK High Time t

sch

66 ns

CDIN to CCLK Rising Setup Time t

dsu

40 ns

CCLK Rising to DATA Hold Time (Note 18) t

15 ns

Rise Time of CCLK and CDIN (Note 19) t

30 ns

Fall Time of CCLK and CDIN (Note 19) t

100 ns

dsu

sch

scl

CCLK

CDIN

css

csh

Figure 3. SPI Control Port Timing

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 31 32

Brak uwag

Cirrus-logic CS4228A Instrukcja Użytkownika Strona 10