Cirrus-logic CS8427 Instrukcja Użytkownika Pobierz pdf (Strona 24)

CS8427

24 DS477F5

OLRCK

OSCLK

SDOUT

Channel A Channel B

Left

Justified

(Out)

OLRCK

OSCLK

Channel A

SDOUT

Channel B

I²S

(Out)

OLRCK

OSCLK

Channel A Channel B

MSB

SDOUT

MSB

LSB

MSB Extended MSB Extended

Right

Justified

(Out)

OLRCK

OSCLK

Channel A

Channel B

MSB

SDOUT

LSB

Channel A

Channel B

LSB

MSB

MSB MSB

AES3

Direct

(Out)

MSB

LSBLSB

MSB

LSB

MSB

LSB

MSB

CUVZCUVZCUVCUV

Frame 191

Frame 0

Figure 16. Serial Audio Output Example Formats

X = don’t care to match format, but does need to be set to the desired setting

* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit

SOMS* SOSF* SORES[1:0]* SOJUST* SODEL* SOSPOL* SOLRPOL*

Left Justified X X XX 0 0 0 0

I²S X X XX 0 1 0 1

Right Justified 1 X XX 1 0 0 0

AES3 Direct X X 11 0 0 0 0

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 59 60

Features 1
General Description 1
TABLE OF CONTENTS 2
LIST OF FIGURES 4
LIST OF TABLES 4
ABSOLUTE MAXIMUM RATINGS 5
TRANSMITTER CHARACTERISTICS 6
SWITCHING CHARACTERISTICS 7
Figure 3. SPI Mode timing 9
Figure 4. I²C Mode timing 10
2. TYPICAL CONNECTION DIAGRAM 11
3. GENERAL DESCRIPTION 12
3.1 Audio Input/Output Ports 12
3.2 Serial Control Port 12
Documents 13
14 DS477F5 14
DS477F5 15 15
16 DS477F5 16
6.5 User Data Handling 17
6.6 Non-Audio Auto Detection 17
7. AES3 TRANSMITTER 18
Status Boundary Timing 18
7.2 TXN and TXP Drivers 18
8. MONO MODE OPERATION 19
8.1 Receiver Mono Mode 19
8.2 Transmitter Mono Mode 19
20 DS477F5 20
22 DS477F5 22
Channel A Channel B 23
Channel A 23
Channel B 23
Frame 191 24
DS477F5 25 25
26 DS477F5 26
7 6 543210 27
11.1 Control 1 (01h) 28
11.2 Control 2 (02h) 28
11.3 Data Flow Control (03h) 29
11.9 Interrupt 1 Mask (09h) 33
11.11 Interrupt 2 Mask (0Ch) 34
13. HARDWARE MODE DESCRIPTION 42
46 DS477F5 46
16. PACKAGE DIMENSIONS 47
17. ORDERING INFORMATION 49
50 DS477F5 50
18.3 AES3 Receiver External 51
Components 51
USER DATA BUFFER MANAGEMENT 52
Management 52
DS477F5 53 53
Two Byte mode 54
19.2.2 Mode 2: Block Mode 54
20.APPENDIX C: PLL FILTER 55
20.1 General 55
20.2.1 General 56
20.2.2 Capacitor Selection 56
20.2.3 Circuit Board Layout 56
20.3.4 Jitter Tolerance 58
20.3.5 Jitter Attenuation 59
21. REVISION HISTORY 60

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