Cirrus-logic CS8420 Instrukcja Użytkownika Strona 21
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- Spis treści
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- Features 1
- General Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 5
- ABSOLUTE MAXIMUM RATINGS 6
- PERFORMANCE SPECIFICATIONS 7
- DC ELECTRICAL SPECIFICATIONS 7
- DIGITAL INPUT CHARACTERISTICS 8
- TRANSMITTER CHARACTERISTICS 8
- SWITCHING CHARACTERISTICS 8
- Figure 3. SPI Mode Timing 10
- - - 100 kHz 11
- 2. TYPICAL CONNECTION DIAGRAM 12
- 3. GENERAL DESCRIPTION 13
- 16 DS245F4 16
- DS245F4 17 17
- 5.1 Dither 18
- Channel A Channel B 20
- Channel A 20
- Channel B 20
- Frame 191 21
- 7.1 AES3 Receiver 22
- 7.1.2 OMCK Out On RMCK 22
- 7.1.5 User Data Handling 23
- 7.2 AES3 Transmitter 24
- 7.2.2 TXN and TXP Drivers 25
- 7.3 Mono Mode Operation 25
- 26 DS245F4 26
- DS245F4 27 27
- 8.1 Sample Rate Converter 28
- 8.2 Non-SRC Delay 29
- 9.1 SPI Mode 30
- 9.2 I²C Mode 31
- 9.3 Interrupts 31
- 7 6543210 32
- 10.4 Data Flow Control (03h) 36
- 7 6 543210 37
- 76543210 43
- AUX3 AUX2 AUX1 AUX0 PRO AUDIO 43
- COPY ORIG 43
- 11.2 Transmitter Startup 48
- 11.3 SRC Invalid State 49
- Power Supply Connections: 51
- Clock-Related Pins: 51
- Overall Device Control: 52
- Audio Input Interface: 52
- Audio Output Interface: 53
- Control Port Signals: 53
- Miscellaneous Pins: 54
- 13. HARDWARE MODES 55
- COMPONENTS 78
- CMOS Gate 79
- 15.1.5 One-Byte Mode 84
- 15.1.6 Two-Byte Mode 84
- 15.2.2 Mode 2: Block Mode 84
- 15.2.4 Mode (3): Reserved 85
- 16. PLL FILTER 87
- 16.2.2 Capacitor Selection 88
- 16.2.3 Circuit Board Layout 88
- 16.3.4 Jitter Tolerance 90
- 16.3.5 Jitter Attenuation 90
- 17. PARAMETER DEFINITIONS 91
- 18. PACKAGE DIMENSIONS 92
- 19. ORDERING INFORMATION 93
- 20. REVISION HISTORY 93
- 94 DS245F4 94
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