Cirrus-logic CDB8422 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS8422Features IEC-60958, AES3/EBU, S/PDIF Inputs–

10 DS692DB2CDB84222.2.4 TDM In to TDM OutThe CS8422’s TDM output performance can be tested by loading the “TDM In to TDM Out” quick setupfile provided

DS692DB2 11CDB84222.3 Software Mode ControlThe CDB8422 may be used with the Microsoft® Windows®-based FlexGUI graphical user interface, allow-ing soft

12 DS692DB2CDB84222.3.1 CS8422 Main Setup TabThe “CS8422 Main Setup” tab provides high-level control of the serial port related registers within theCS

DS692DB2 13CDB84222.3.2 CS8422 Receiver Controls and Status TabThe “CS8422 Receiver Controls and Status” tab provides high-level control of the CS8422

14 DS692DB2CDB84222.3.3 CS8422 Interrupt Controls and Status TabThe “CS8422 Interrupt Controls and Status” tab provides high-level control of the CS84

DS692DB2 15CDB84222.3.4 FPGA Controls TabThe “FPGA Controls” tab provides high-level control of the on-board FPGA’s register settings. This tabprovide

16 DS692DB2CDB84222.3.5 Register Maps TabThe Register Maps tabs provide low-level control of the CS8422, FPGA, and GPIO register settings. Reg-ister v

DS692DB2 17CDB84222.4 FPGA Register Quick ReferenceThis table shows the register names and their associated default values.2.5 FPGA Register Descripti

18 DS692DB2CDB84222.5.2.3 AUX MCLK Source (AUX_Mclk)Default = 0Function:This bit controls the source of the auxiliary MCLK signal. If the CS8422’s GPO

DS692DB2 19CDB84222.5.3.3 SAO2 Subclock Source (SAO2_MS)Default = 00Function:These bits control the direction of the LRCK and SCLK signals between the

2 DS692DB2CDB8422TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

20 DS692DB2CDB84222.5.4.3 User Data (UBIT_IN)Default = 0Function:This bit controls the state of the user data bit for the CS8406’s output S/PDIF data.

DS692DB2 21CDB84222.5.5 CS8406 Control 2 (Address 05h)2.5.5.1 CS8406 Reset Pin (8406_RST)Default = 1Function:This bit controls the state of the CS8406

22 DS692DB2CDB84223. HARDWARE MODEPowering up the CDB8422 without a USB connection to a PC operates the evaluation board in hardware mode. Inthis mode

DS692DB2 23CDB84223.2 Configuration OptionsIn hardware mode, to configure the CDB8422 for making performance measurements, one needs to usethe on-boar

24 DS692DB2CDB84223.2.2 TDM In to TDM OutThe CS8422’s TDM output performance can be tested by setting the hardware switches as shown inTable 2. This c

DS692DB2 25CDB84223.3 Hardware Mode ControlThis section provides a full description for the hardware mode control switches S3, S4, and S7, see the ta-

26 DS692DB2CDB8422Switch S4 controls the data format options for both serial output ports, see Table 4 for switch configurations.For SDOUT2, the outpu

DS692DB2 27CDB8422Switch S7 controls the remaining options for the CS8422 in hardware mode, see Table 5 for switch config-urations. The NV/RERR (CS842

28 DS692DB2CDB84224. SYSTEM CONNECTIONS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT+5V J2 Input+5 V Power SupplyGND J3 InputGround ReferenceUSB I/O J

DS692DB2 29CDB84225. JUMPER SETTINGSNote: All settings denoted by an asterisk (*) are the Default Factory Settings.Note: If a S/PDIF source is connec

DS692DB2 3CDB84225. JUMPER SETTINGS ...

30 DS692DB2CDB84227. CDB8422 BLOCK DIAGRAMFigure 14. Block DiagramCS8406CS8422RX InputTX OutputCanned OscillatorCrystal OscillatorJumperILRCKISCLKSDI

31 DS692DB2CDB84228. CDB8422 SCHEMATICSFigure 15. CS8422 & XTI (Schematic Sheet 1)

32 DS692DB2CDB8422Figure 16. RX Inputs (Schematic Sheet 2)

33 DS692DB2CDB8422Figure 17. PCM Input Header (Schematic Sheet 3)

34 DS692DB2CDB8422Figure 18. HW Mode Control (Schematic Sheet 4)

35 DS692DB2CDB8422Figure 19. FPGA (Schematic Sheet 5)

36 DS692DB2CDB8422Figure 20. MCLK Routing (Schematic Sheet 6)

37 DS692DB2CDB8422Figure 21. Serial Audio 1 Output Header (Schematic Sheet 7)

38 DS692DB2CDB8422Figure 22. Serial Audio 2 Output Header (Schematic Sheet 8)

39 DS692DB2CDB8422Figure 23. TDM Header (Schematic Sheet 9)

4 DS692DB2CDB84221. SYSTEM OVERVIEWThe CDB8422 platform provides S/PDIF and AES3/EBU digital interfaces to the CS8422 and allows for externalDSP and I

40 DS692DB2CDB8422Figure 24. CS8406 and Auxiliary TX (Schematic Sheet 10)

41 DS692DB2CDB8422Figure 25. USB and MCU (Schematic Sheet 11)

42 DS692DB2CDB8422Figure 26. Power (Schematic Sheet 12)

43 DS692DB2CDB84229. CDB8422 LAYOUTFigure 27. Silk Screen

44 DS692DB2CDB8422Figure 28. Top-Side Layer

45 DS692DB2CDB8422Figure 29. Bottom-Side Layer

46 DS692DB2CDB842210.REVISION HISTORYRevision ChangesDB1 Initial ReleaseDB2 Added S/PDIF receiver sensitivity note to Section 1.8 on page 5.Changed 0.

DS692DB2 5CDB8422When the evaluation board is not connected to a PC, the CS8422 is placed in hardware mode and is con-figured using DIP switches. Cert

6 DS692DB2CDB84222. SOFTWARE MODEConnecting a USB port cable from a PC to the USB connector (J37) on the CDB8422 and launching the providedgraphical u

DS692DB2 7CDB84222.2 Configuration OptionsIn software mode, to configure the CDB8422 for making performance measurements, one needs to use Cir-rus Log

8 DS692DB2CDB84222.2.2 AES3/EBU In to S/PDIF and PCM OutThe CS8422’s AES3/EBU receiver and SRC output performance can be tested by loading the “AES3 I

DS692DB2 9CDB84222.2.3 PCM In to S/PDIF and PCM OutThe CS8422’s serial input port and SRC output performance can be tested by loading the “PCM In toSP