Cirrus-logic CS43L21 Instrukcja Użytkownika Pobierz pdf (Strona 5)

DS723F1 5

CS43L21

Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34

Figure 19.Control Port Timing, I²C Write ................................................................................................... 35

Figure 20.Control Port Timing, I²C Read ................................................................................................... 35

Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16  load) .................................................... 55

Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16  load) .................................................... 55

Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32  load) .................................................... 56

Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32  load) .................................................... 56

Figure 25.Power Dissipation vs. Output Power into Stereo 16 

Figure 26.Power Dissipation vs. Output Power into Stereo 16 (Log Detail) .......................................... 57

Figure 27.Passband Ripple ....................................................................................................................... 61

Figure 28.Stopband ................................................................................................................................... 61

Figure 29.Transition Band ......................................................................................................................... 61

Figure 30.Transition Band (Detail) ............................................................................................................ 61

LIST OF TABLES

Table 1. I/O Power Rails ............................................................................................................................. 8

Table 2. Hardware Mode Feature Summary ............................................................................................. 23

Table 3. MCLK/LRCK Ratios .................................................................................................................... 29

1 2 3 4 5 6 7 8 9 10 ... 63 64

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