Cirrus-logic CS43L22 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comMARCH '10DS792F2Low Power, Stereo DAC w/Headphone & Speaker Amps

10 DS792F2CS43L22Confidential Draft3/4/103. CHARACTERISTIC AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSAGND=DGND=0 V, all voltages with respect

DS792F2 11CS43L22Confidential Draft3/4/10ANALOG OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale

12 DS792F2CS43L22Confidential Draft3/4/105. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re-quired for t

DS792F2 13CS43L22Confidential Draft3/4/10PWM OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full scale 99

14 DS792F2CS43L22Confidential Draft3/4/106. The PWM driver should be used in captive speaker systems only.7. Optimal PWM performance is achieved when

DS792F2 15CS43L22Confidential Draft3/4/10LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICSTest conditions (unless otherwise specified): Input test signal is a

16 DS792F2CS43L22Confidential Draft3/4/10SWITCHING SPECIFICATIONS - SERIAL PORTInputs: Logic 0 = DGND; Logic 1 = VL. 11. After powering up the CS43L22

DS792F2 17CS43L22Confidential Draft3/4/10SWITCHING SPECIFICATIONS - I²C CONTROL PORTInputs: Logic 0 = DGND; Logic 1 = V; SDA CL=30pF.13. Data must be

18 DS792F2CS43L22Confidential Draft3/4/10DC ELECTRICAL CHARACTERISTICS AGND = 0 V; all voltages with respect to ground. 14. Valid with the recommende

DS792F2 19CS43L22Confidential Draft3/4/10POWER CONSUMPTION See (Note 16)16. Unless otherwise noted, test conditions are as follows: All zeros input, S

2 DS792F2CS43L22Confidential Draft3/4/10System Features 12, 24, and 27 MHz Master Clock Support in Addition to Typical Audio Clock Rates High Perfor

20 DS792F2CS43L22Confidential Draft3/4/104. APPLICATIONS4.1 Overview4.1.1 Basic ArchitectureThe CS43L22 is a highly integrated, low power, 24-bit audi

DS792F2 21CS43L22Confidential Draft3/4/104.2 DSP Engine Referenced Control Register LocationDSPDEEMPH...PCMxMUTE ...

22 DS792F2CS43L22Confidential Draft3/4/104.2.1 Beep GeneratorThe Beep Generator generates audio frequencies across approximately two octave major scal

DS792F2 23CS43L22Confidential Draft3/4/10the thresholds. Referenced Control Register LocationLimiter Controls... Master Volume Contro

24 DS792F2CS43L22Confidential Draft3/4/104.3 Analog PassthroughThe CS43L22 accommodates analog routing of the analog input signal directly to the head

DS792F2 25CS43L22Confidential Draft3/4/104.4 Analog OutputsReferenced Control Register LocationAnalog OutputHPxMUTE ...HPxVOL[

26 DS792F2CS43L22Confidential Draft3/4/104.5 PWM OutputsNote: The PWM speaker amplifiers should not be used in the 384x MCLK modes (18.4320 and16.9344

DS792F2 27CS43L22Confidential Draft3/4/104.5.1 Mono Speaker Output ConfigurationThe CS43L22 accommodates a stereo as well as a mono speaker output con

28 DS792F2CS43L22Confidential Draft3/4/10 Referenced Control Register LocationVPREF ...SPKxVOL...

DS792F2 29CS43L22Confidential Draft3/4/104.6 Serial Port ClockingThe CS43L22 serial audio interface port operates either as a slave or master, determi

DS792F2 3CS43L22Confidential Draft3/4/10TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS792F2CS43L22Confidential Draft3/4/10Note: *The marked sample rate values are not exact representations of the actual frame clock frequencyThey ha

DS792F2 31CS43L22Confidential Draft3/4/104.7.1 DSP ModeIn DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) inp

32 DS792F2CS43L22Confidential Draft3/4/104. Wait at least 100 µs. The device will be fully powered down after this 100 µs delay. Prior to the removal

DS792F2 33CS43L22Confidential Draft3/4/105. CONTROL PORT OPERATIONThe control port is used to access the registers allowing the CS43L22 to be configur

34 DS792F2CS43L22Confidential Draft3/4/10Send start condition. Send 10010100 (chip address & write operation). Receive acknowledge bit. Send MAP b

DS792F2 35CS43L22Confidential Draft3/4/106. REGISTER QUICK REFERENCEDefault values are shown below the bit names. Unless otherwise specified, all “Res

36 DS792F2CS43L22Confidential Draft3/4/1020h Master A Vol MSTAVOL7 MSTAVOL6 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1 MSTAVOL0p51 000 0000021h Mast

DS792F2 37CS43L22Confidential Draft3/4/107. REGISTER DESCRIPTIONAll registers are read/write except for the chip I.D. and Revision Register and Interr

38 DS792F2CS43L22Confidential Draft3/4/107.3 Power Control 2 (Address 04h)7.3.1 Headphone Power ControlConfigures how the SPK/HP_SW pin, 6, controls t

DS792F2 39CS43L22Confidential Draft3/4/107.4.2 Speed ModeConfigures the speed mode of the DAC in Slave Mode and sets the appropriate MCLK divide ratio

4 DS792F2CS43L22Confidential Draft3/4/107.2.1 Power Down ...

40 DS792F2CS43L22Confidential Draft3/4/107.4.6 MCLK Divide By 2Divides the input MCLK by 2 prior to all internal circuitry. Note: In Slave Mode, this

DS792F2 41CS43L22Confidential Draft3/4/107.5.5 Audio Word LengthConfigures the audio sample word length used for the data into SDIN.Note: When the int

42 DS792F2CS43L22Confidential Draft3/4/107.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h)7.7.1 Passthrough Input Channel MappingSele

DS792F2 43CS43L22Confidential Draft3/4/107.10 Playback Control 1 (Address 0Dh)7.10.1 Headphone Analog GainSelects the gain multiplier for the headphon

44 DS792F2CS43L22Confidential Draft3/4/107.11 Miscellaneous Controls (Address 0Eh)7.11.1 Passthrough AnalogConfigures an analog passthrough from the a

DS792F2 45CS43L22Confidential Draft3/4/107.11.6 Digital Zero CrossConfigures when the signal level changes occur for the digital volume controls. Note

46 DS792F2CS43L22Confidential Draft3/4/107.12.5 Speaker MONO ControlConfigures a parallel full bridge output for the speaker channels. 7.12.6 Speaker

DS792F2 47CS43L22Confidential Draft3/4/107.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)7.14.1 PCM Channel x MuteConfigures a digital mu

48 DS792F2CS43L22Confidential Draft3/4/10Notes:1. This setting must not change when BEEP is enabled.2. Beep frequency will scale directly with sample

DS792F2 49CS43L22Confidential Draft3/4/10Notes:1. This setting must not change when BEEP is enabled.2. Beep off time will scale inversely with sample

DS792F2 5CS43L22Confidential Draft3/4/107.16 Beep Volume & Off Time (Address 1Dh) ...

50 DS792F2CS43L22Confidential Draft3/4/107.17.3 Treble Corner Frequency Sets the corner frequency (-3 dB point) for the treble shelving filter.7.17.4

DS792F2 51CS43L22Confidential Draft3/4/107.18.2 Bass Gain Sets the gain of the bass shelving filter. 7.19 Master Volume Control: MSTA (Address 20h) &

52 DS792F2CS43L22Confidential Draft3/4/107.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)7.21.1 Speaker Volume Control Sets th

DS792F2 53CS43L22Confidential Draft3/4/107.23 Limiter Control 1, Min/Max Thresholds (Address 27h)7.23.1 Limiter Maximum Threshold Sets the maximum lev

54 DS792F2CS43L22Confidential Draft3/4/107.23.4 Limiter Zero Cross DisableConfigures an override of the digital zero cross setting. 7.24 Limiter Cont

DS792F2 55CS43L22Confidential Draft3/4/107.25 Limiter Attack Rate (Address 29h)7.25.1 Limiter Attack Rate Sets the rate at which the limiter applies d

56 DS792F2CS43L22Confidential Draft3/4/107.26.3 PCMx Overflow (Read Only)Indicates the over-range status in the PCM data path. 7.27 Battery Compensat

DS792F2 57CS43L22Confidential Draft3/4/107.27.3 VP ReferenceSets the desired VP reference used for battery compensation. 7.28 VP Battery Level (Addres

58 DS792F2CS43L22Confidential Draft3/4/107.29.2 SPKR/HP Pin Status (Read Only)Indicates the status of the SPKR/HP pin. 7.30 Charge Pump Frequency (Ad

DS792F2 59CS43L22Confidential Draft3/4/108. ANALOG PERFORMANCE PLOTS8.1 Headphone THD+N versus Output Power PlotsTest conditions (unless otherwise spe

6 DS792F2CS43L22Confidential Draft3/4/1011. DIGITAL FILTER PLOTS ...

60 DS792F2CS43L22Confidential Draft3/4/10 G = 0.6047G = 0.7099G = 0.8399G = 1.0000G = 1.1430Legend-100-20-95-90-85-80-75-70-65-60-55-50-45-40-35-30

DS792F2 61CS43L22Confidential Draft3/4/109. EXAMPLE SYSTEM CLOCK FREQUENCIES *The”MCLKDIV2” bit must be enabled.9.1 Auto Detect Enabled 9.2 Auto D

62 DS792F2CS43L22Confidential Draft3/4/1010.PCB LAYOUT CONSIDERATIONS10.1 Power Supply, GroundingAs with any high-resolution converter, the CS43L22 re

DS792F2 63CS43L22Confidential Draft3/4/1011.DIGITAL FILTER PLOTSFigure 22. Passband Ripple Figure 23. StopbandFigure 24. DAC Transition Band Figure

64 DS792F2CS43L22Confidential Draft3/4/1012.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spe

DS792F2 65CS43L22Confidential Draft3/4/1013.PACKAGE DIMENSIONS1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies t

66 DS792F2CS43L22Confidential Draft3/4/1014.ORDERING INFORMATION15.REFERENCES1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January

DS792F2 7CS43L22Confidential Draft3/4/101. PIN DESCRIPTIONSPin Name # Pin DescriptionSDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I

8 DS792F2CS43L22Confidential Draft3/4/101.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table

DS792F2 9CS43L22Confidential Draft3/4/102. TYPICAL CONNECTION DIAGRAMNote 3Note 2Note 11 µF+1.8 V to +2.5 V0.1 µF1 µFDGNDVL0.1 µF+1.8 V to +3.3 VSCLSD