Cirrus-logic AN269 Instrukcja Użytkownika Pobierz pdf (Strona 14)

14 AN269REV1

AN269

In the third SPCLK for 2 2/3 mode, pixel 5’s Green and Red components will be clocked out of P[1:0]. All of the Red,

Green, and Blue components of pixel 6 are clocked out of P[4:2]. Pixel 7’s Red, Green, and Blue components are

clocked out of P[7:5]. On successive SPCLK periods, the pattern of pixels will repeat.

Pixel Data Bus

Pins P[17:0]

Pixels 5, 6 and 7 (Third SPCLK)

Pixel Data Most Significant Bits

(from LUT and Blink Logic)

Figure 7. 3-Bits Per Pixel Formatted as 2-2/3 Bits, Third SPCLK

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 64 65

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Cirrus-logic AN269 Instrukcja Użytkownika Strona 14