Cirrus-logic AN269 Instrukcja Użytkownika Pobierz pdf (Strona 13)

AN269

AN269REV1 13

In the second SPCLK for 2-2/3 mode, pixel 2’s Red component will be clocked out of P[0]. All of the Red, Green,

and Blue components of pixel 3 are clocked out of P[3:1]. Pixel 4’s Red, Green, and Blue components are clocked

out of P[6:4]. Note that ONLY the Blue component of Pixel 5 is clocked out of P[7]. The Green and Red components

of pixel 5 will be clocked out during the third SPCLK.

Pixel Data Bus

Pins P[17:0]

Pixels 2, 3, 4 and 5 (Second SPCLK)

Pixel Data Most Significant Bits

(from LUT and Blink Logic)

Figure 6. 3-Bit Per Pixel Formatted as 2 2/3 Bits, Second SPCLK

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 64 65

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Cirrus-logic AN269 Instrukcja Użytkownika Strona 13