Cirrus-logic CS4348 Instrukcja Użytkownika Pobierz pdf (Strona 11)

CS4344/5/8

3. TYPICAL CONNECTION DIAGRAM

Figure 6. Typical Connection Diagram

DEM/SCLK

Audio

Data

Processor

External Clock

MCLK

AGND

AOUTR

CS4344

CS4345

CS4348

SDIN

LRCK

AOUTL

0.1 µF

1µF

Left Audio

Output

Right Audio

Output

+3.3 V to +5 V

3.3 µF

10 k



470

R + 470



Fs(R 470)

ext

3.3 µF

10 k



470



ext

0.1 µF

µF

*3.3

µF

FILT+

Note*

Note* = This circuitry is intended for applications where the

CS4344/5/8 connects directly to an unbalanced output of

the design. For internal routing applications please see the

DAC analog output characteristics for loading limitations.

For best 20 kHz response

µF*10

*Popguard ramp can be adjusted by

selecting this capacitor value to be

3.3 µF to give 250 ms ramp time

or 10 µF to give a 420 ms ramp

time.

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 23 24

CS4344/5/8 1
1. PIN DESCRIPTIONS 4
ABSOLUTE MAXIMUM RATINGS 5
DAC ANALOG CHARACTERISTICS 6
DIGITAL INPUT CHARACTERISTICS 8
3. TYPICAL CONNECTION DIAGRAM 11
4. APPLICATIONS 12
5. FILTER PLOTS 18
6. PARAMETER DEFINITIONS 21
7. PACKAGE DIMENSIONS 22
8. ORDERING INFORMATION 23
9. REVISION HISTORY 24

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