Cirrus-logic CS4234 Instrukcja Użytkownika Strona 45
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DS899F1 45
CS4234
Two control parameters allow the user to limit the ramp-rate range to achieve optimum effect. The MIN
DELAY[2:0] setting limits the maximum ramp rate; higher values will introduce more lag in the envelope
tracking while providing a smoother ramp. The MAX DELAY[2:0] setting limits the minimum ramp rate;
lower values will permit closer tracking of the envelope but may reintroduce zipper noise. The default val-
ues of these registers are recommended as a starting point. It is possible to disable the volume envelope
tracking and always produce a constant ramp rate. To accomplish this, set the MIN DELAY[2:0] and MAX
DELAY[2:0] values to match the MUTE DELAY[1:0] setting.
The envelope counter time out period which defines the boundary between the two soft-ramping behav-
iors depends on the base rate. It is equal to approximately 100,000/Fs.
The MUTE DELAY[1:0], MIN DELAY[2:0], and MAX DELAY[2:0] bits specify a delay equal to a multiple
of the base period between volume steps of
6.02
/
64
dB, which is approximately 0.1 dB. This is the internal
resolution of the volume control engine. Consequently the soft-ramp rate can be expressed in ms/dB as
shown in Table 8.
USER: Change
Volume or Mute
Register
Wait State
Envelope Counter
Running
Envelope
Counter
Timed Out?
Yes
No
Reset Envelope
Counter
Limit Ramp Rate
Reset Envelope
Counter
Ramp Rate =
MUTE_DELAY
Changes VolumeBetween Time
Setting VolumeCurrent - Setting Volume New
Rate Ramp
MIN_DELAY
MAX_DELAY
Figure 30. Soft Ramp Behavior
- DAC Features 1
- ADC Features 1
- System Features 1
- Class H Controller Features 1
- Common Applications 1
- General Description 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. PIN DESCRIPTIONS 6
- 1.1 I/O Pin Characteristics 7
- DS899F1 8 8
- ABSOLUTE MAXIMUM RATINGS 9
- TYPICAL CURRENT CONSUMPTION 11
- ANALOG INPUT CHARACTERISTICS 12
- CS4234 AINx 13
- DS899F1 13 13
- CS4234 AINx + 13
- 25000/Fs 14
- ANALOG OUTPUT CHARACTERISTICS 15
- DIGITAL I/O CHARACTERISTICS 17
- DS899F1 19 19
- 4. APPLICATIONS 21
- 4.2.2 Power-down 22
- DS899F1 23 23
- 4.2.3 DAC DC Loading 24
- 4.3 I²C Control Port 25
- 4.3.1.1 Map Increment (INCR) 26
- 4.4 System Clocking 26
- 4.4.1 Master Clock 26
- 4.4.3 Slave Mode Clock Ratios 27
- 4.5 Serial Port Interface 28
- 4.5.1 TDM Mode 28
- 32-Bit Channel Block 29
- 24-Bit Audio Word 29
- 8-Bit Zero Pad 29
- (Or DAC5 Data) 29
- DS899F1 30 30
- 4.6 Internal Signal Path 32
- 4.6.1.1 ADC Signal Routing 32
- 4.6.2 ADC Path 38
- 4.6.2.1 Analog Inputs 38
- 4.6.2.2 ADC HPF 38
- 4.6.3 DAC1-4 Path 39
- 4.6.3.1 De-emphasis Filter 39
- 4.6.4 Low-Latency Path 40
- 4.6.5 DAC5 Path 41
- 4.6.5.4 De-emphasis Filter 42
- 4.6.5.5 Filter Options 42
- 4.6.6 Volume Control 42
- 4.6.6.1 Mute Behavior 43
- 4.6.6.2 Soft Ramp 44
- MIN_DELAY 45
- MAX_DELAY 45
- 4.6.6.3 Noise Gate 46
- 4.7 Reset Line 47
- 4.8.1 Interrupt Masking 47
- DS899F1 49 49
- 5. REGISTER QUICK REFERENCE 50
- DS899F1 51 51
- 6. REGISTER DESCRIPTIONS 52
- 6.3.1 Base Rate Advisory 53
- 6.3.2 Speed Mode 53
- 6.3.3 Master Clock Rate 53
- 6.4.1 Output Sample Width 54
- 6.4.2 Input Sample Width 54
- 6.4.4 DAC5 Sample Width 54
- 7654321 0 55
- 6.6.1 DAC1-4 Data Source 56
- 6.6.2 Low-latency Path Source 56
- 6.7.1 SDIN1 Mask 1 57
- 6.8.1 SDIN1 Mask 2 57
- 6.9.1 SDIN2 Mask 1 58
- 6.10.1 SDIN2 Mask 2 58
- 76543210 59
- 6.11.3 Group Delay 60
- 6.12.1 VA Select 60
- 6.12.3 Invert ADCx 60
- DS899F1 61 61
- Mutes the ADCx signal 61
- Powers down the ADCx path 61
- 6.15.1 DAC1-4 Noise Gate 62
- 6.15.2 DAC1-4 De-emphasis 62
- 6.15.3 DAC5 De-emphasis 62
- 6.19.1 Mute Delay 65
- 6.19.2 Minimum Delay 65
- 6.19.3 Maximum Delay 65
- 6.20.1 x Volume Control 66
- 6.21.1 INT MODE 66
- 6.21.2 Interrupt Pin Polarity 66
- 6.25.1 DACx Clip 69
- 7. ADC FILTER PLOTS 70
- 8. DAC FILTER PLOTS 71
- DS899F1 72 72
- 9. PACKAGE DIMENSIONS 73
- 10.ORDERING INFORMATION 74
- DS899F1 75 75
- 11.1 Voltage Headroom 76
- 11.2 Lead Time 76
- 11.3 Gain Matching 76
- 11.4 SMPS (TPS) Modes 77
- DS899F1 78 78
- 12.REVISION HISTORY 79
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