Cirrus-logic CDB43L21 Instrukcja Użytkownika

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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
Evaluation Board for the CS43L21
Features
MUX’d Analog Output
Stereo RCA Output (w/Optional Load or
LPF)
Stereo Headphone Jack
Mono Speaker Driver w/Banana Posts
8 kHz to 96 kHz S/PDIF Interface
CS8415 Digital Audio Receiver
I/O Stake Headers
External Control Port Accessibility
External DSP Serial Audio I/O Accessibility
Independent, Regulated Supplies
1.8 V to 3.3 V Logic Interface
Hardware Control
11 Pre-Defined Switch Settings
FlexGUI S/W Control - Windows
®
Compatible
Pre-Defined & User-Configurable Scripts
Layout and Grounding Recommendations
Description
The CDB43L21 evaluation board is an excellent means
for evaluating the CS43L21 DAC. Evaluation requires a
digital signal source, analog analyzer, and power sup-
plies. Optionally, a Windows
PC-compatible computer
may be used to evaluate the CS43L21 in Software
Mode.
System timing can be provided by the CS8415, by the
CS43L21 with supplied master clock, or by an I/O stake
header with a DSP connected.
RCA phono jacks are provided for the CS43L21 analog
outputs. 1/8th inch jacks are also available for head-
phone output. Digital data input is available via RCA
phono or optical connectors to the CS8415.
The Windows software provides a Graphical User Inter-
face (GUI) to make configuration of the CDB43L21
easy. The software communicates through the PC’s se-
rial port/USB to configure the control port registers so
that all the features of the CS43L21 can be evaluated.
The evaluation board may also be configured to accept
external timing and data signals for operation in a user
application during system development.
ORDERING INFORMATION
CDB43L21 Evaluation Board
Analog Output
(Line + Headphone)
Software Mode
Control Port
CS43L21
S/PDIF Input
(CS8415)
Clocks/Data Header
I²C/SPI Header
FPGA
Oscillator
(socket)
Reset
MCLK
Reset
Reset
MCLK
Reset
Hardware Mode
Switches
JANUARY '08
DS723DB1
CDB43L21
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Podsumowanie treści

Strona 1 - CDB43L21

Copyright © Cirrus Logic, Inc. 2008(All Rights Reserved)http://www.cirrus.comEvaluation Board for the CS43L21Features MUX’d Analog Output– Stereo RCA

Strona 2

10 DS723DB1CDB43L212.3 Register Maps TabThe Advanced Register Debug tab provides low-level control of the CS43L21 individual register settings.Registe

Strona 3

DS723DB1 11CDB43L213. HARDWARE MODE CONTROLThe CDB may be configured without the use of a software control port through the use of two switches, “FPGA

Strona 4 - 1. SYSTEM OVERVIEW

12 DS723DB1CDB43L21OscillatorMCLKLRCK/SCLKSDINCS43L21I/O HeaderMCLKLRCK/SCLKSDINCS8415RMCK(256Fs)OLRCK/OSCLKSDOUT(LJ)OscillatorMCLKLRCK/SCLKSDINCS43L2

Strona 5

DS723DB1 13CDB43L21Figure 8. Routing 5MCLKLRCK/SCLKSDINCS43L21I/O HeaderMCLKLRCK/SCLKSDINCS8415RMCK(256Fs)OLRCK/OSCLKSDOUT(LJ)Oscillator

Strona 6

14 DS723DB1CDB43L214. SYSTEM CONNECTIONS 5. JUMPER SETTINGSCONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT+5V J26 Input +5.0 V Power SupplyGND J27 Input G

Strona 7 - 2. SOFTWARE MODE CONTROL

DS723DB1 15CDB43L216. CDB43L21 BLOCK DIAGRAM Figure 9. Block DiagramAnalog Output(Line + Headphone)Software Mode Control Port CS43L21S/PDIF Input (CS

Strona 8

16 DS723DB1CDB43L217. CS43L21 SCHEMATICSFigure 10. CS43L21 and Analog I/O (Schematic Sheet 1)

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DS723DB1 17CDB43L21 Figure 11. S/PDIF I/O (Schematic Sheet 2)

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18 DS723DB1CDB43L21Figure 12. FPGA (Schematic Sheet 3)

Strona 11 - 3. HARDWARE MODE CONTROL

DS723DB1 19CDB43L21Figure 13. Level Shifters & I/O Stake Header (Schematic Sheet 4)

Strona 12

2 DS723DB1CDB43L21TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

Strona 13

20 DS723DB1CDB43L21Figure 14. Control Port I/O (Schematic Sheet 5)

Strona 14 - 5. JUMPER SETTINGS

DS723DB1 21CDB43L21Figure 15. Power (Schematic Sheet 6)

Strona 15 - 6. CDB43L21 BLOCK DIAGRAM

22 DS723DB1CDB43L218. CDB43L21 LAYOUTFigure 16. Silk ScreenCDB43L21CS43L21CS43L21CS43L21

Strona 16 - 7. CS43L21 SCHEMATICS

DS723DB1 23CDB43L21Figure 17. Top-Side Layer

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24 DS723DB1CDB43L21Figure 18. Bottom-Side Layer

Strona 18

DS723DB1 25CDB43L219. ERRATAThe CDB43L21 currently does not support the +1.8 V and +2.5 V power supply options on header J31 (VL). Thisheader must be

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DS723DB1 3CDB43L219. ERRATA ...

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4 DS723DB1CDB43L211. SYSTEM OVERVIEW The CDB43L21 evaluation board is an excellent means for evaluating the CS43L21. Digital audio signal interfacesar

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DS723DB1 5CDB43L21Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 11 provideconfiguration details.1.5 CS84

Strona 22 - 8. CDB43L21 LAYOUT

6 DS723DB1CDB43L211.9 Stand-Alone Switches The “FPGA H/W Control” and “CS43L21 H/W Control” switches control all Hardware Mode options.Section 3. “Har

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DS723DB1 7CDB43L212. SOFTWARE MODE CONTROLThe CDB43L21 may be used with the Microsoft® Windows-based FlexGUI graphical user interface, allowing soft-w

Strona 24

8 DS723DB1CDB43L212.1 General Configuration TabThe “General Configuration” tab provides high-level control of signal routing on the CDB43L21. This tab

Strona 25 - 10.REVISION HISTORY

DS723DB1 9CDB43L212.2 DAC Volume Controls TabThe “DAC Volume Controls” tab provides high-level control of all volume settings in the CS43L21. Statuste

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