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EP7309/11/12 User’s Manual - DS508UM4 5-3
Copyright Cirrus Logic, Inc. 2003
System Registers
55
5
Operational Overview
Most of the functions represented in the SYSCON and SYSFLG registers are either
described thoroughly in other chapters or require little explanation. Below is a
detailed explanation of those that do not get covered sufficiently elsewhere in this
manual.
Buzzer
The BUZ output pin on the EP73xx is intended as a signal source for a basic
annunciator. Two hardware sources and one software source are available for
controlling the frequency of the signal. In software mode, the
BUZ output reflects the
state of the BZTOG bit in SYSCON1. It is the responsibility of the software executing
on the EP73xx to toggle BZTOG at the desired frequency. Software mode can be used
to generate audio tones with a controlled volume by varying the duty cycle of the
pulse that BZTOG is fed. BZMOD must be cleared to enable the use of BZTOG.
Choices of hardware sources for
BUZ include the timer clock and the output of on-
chip timer TC1. BUZFREQ selects between these two hardware sources. When
BUZFREQ is cleared, the buzzer is generated from the TC1 timer underflow bit. The
output changes every time the timer wraps around. The frequency depends on how
timer TC1 is configured. Prescale mode for timer TC1 provides the greatest flexibility
in the selection of a frequency for
BUZ.SeeChapter 3 for a detailed description of
programming the timers. If BUZFREQ is set, then a 500 Hz internal timer is fed to
BUZ. Note that in the externally clocked 13 MHz mode, this clock will be 528 Hz
unless the OSTB bit (bit 12) in SYSCON2 is set.
BUZ is also used to created MCLK for external CODECs when the DAIis enabled. For
annunciator applications,
BUZ for MCLK in the DAI must be disabled.
Debug Mode
Settingthe debugmode bit in the SYSCON1 register allows internal memory accesses
that would normally not be represented to appear on the external memory bus. In
addition, the clock for this bus as well as the two interrupt signals that are generated
by the interrupt controllerare output on Port E.
When in debug mode,
nCS5 becomes the address strobe for the internal accesses in
addition to its usual function as an external memory strobe. External memory
accesses to the 0x5000.0000-0x5FFF.FFFF range will still cause
nCS5 to assert in
addition to internal memory accesses.
The nFIQ and nIRQ signals between the interrupt controller and the ARM720T core
will appear on Port E pins when debug mode is enabled.
PE1 will represent the state
of nIRQ, and
PE2 will represent nFIQ. To aid in following memory accesses, PE0 will
outputtheinternalbusclock. Using theseextrasignalsrequiresthatthedata direction
bits for Port E pins
PE0-PE2 must be set to output.
- EP73xx User’s Guide 1
- 1Contents 4
- Chapter 5. System Registers 5
- Chapter 6. Processor Support 6
- Chapter 7. SDRAM Controller 6
- Chapter 9. LCD Interface 6
- Appendix A. Boot Code 8
- Contents 9
- List of Figures 10
- List of Tables 12
- Chapter 1 15
- 1Introduction 15
- Overview 15
- Memory Map and Register List 16
- Internal Register Map 17
- Pin Description 20
- External Signal Functions 21
- Output Bi-Directional Pins 24
- Block Diagrams 25
- References 26
- Chapter 2 27
- 2CPU Core 27
- Programming Register List 27
- Programming Examples 28
- CPU Core 29
- Write Buffer 32
- CPU Register Definitions 33
- User FIQ IRQ SVC Undef Abort 34
- CPU Clocks 35
- On-Chip PLL 36
- PLL Register Descriptions 37
- CPU State Control 38
- Idle State 39
- Power Up Sequence 40
- Table 3-1: Timer Registers 43
- Timer Register Descriptions 45
- Chapter 4 47
- 4Interrupt Controller 47
- Interrupt Register List 47
- Interrupt Operation 50
- Interrupt Listing 51
- Operating State 52
- Standby State 53
- Interrupt Controller 54
- End-Of-Interrupt Locations 59
- Chapter 5 61
- 5System Registers 61
- System Register List 62
- MaverickKey 64
- Unique-ID 64
- BUZ output reflects 65
- EXPCLK is 66
- System Registers 68
- 0032-bit 71
- 1016-bit 71
- 11Reserved 71
- CLKSEL (PE[2])input,latched 72
- Chapter 6 75
- 6Processor Support 75
- Internal Boot Mode 76
- External Boot Mode 76
- CS0 and the 77
- Endianess 78
- Endian Byte Addressing 79
- Processor Support 80
- Chapter 7 81
- 7SDRAM Controller 81
- SDRAM Register List 81
- SDRAM Register Descriptions 83
- SDRAM Controller 84
- SRAM/Expansion Bus Controller 89
- Chapter 9 91
- 9LCD Interface 91
- LCD Register List 91
- LCD DMA Controller 93
- Gray Scale 94
- 4 Bits per pixel 95
- 2 Bits per pixel 95
- 1 Bit per pixel 95
- Hardware Interface 96
- Color LCDs 96
- LCD Register Descriptions 97
- (PALMSW) 98
- FBADDR) 99
- LCD Interface 100
- Operational Overview 102
- Keyboard Interface 103
- Chapter 11 105
- 11General Purpose I/O (GPIO) 105
- Introduction 105
- Features 105
- Programming Example 106
- Register Descriptions 106
- Chapter 12 107
- 12PWM Interface 107
- Block Diagram 107
- PWM Register Descriptions 109
- PWM Interface 110
- PD0 / LEDFLSH)tobetoggledata 111
- Register Definitions 112
- Chapter 14 113
- 14JTAG Interface 113
- Boundary Scan 114
- Debug Modes 115
- Debug/ICE Test Mode 116
- Hi-Z (System) Test Mode 116
- JTAG Interface 117
- ADCCLK) 121
- Bit Descriptions: 122
- (SYNCIO[6:0]) 123
- SSI Port 124
- Chapter 16 125
- 16DAI/CODEC/SSI2 125
- DAI/CODEC/SSI2 Register List 126
- DAI Interface 128
- DAI Clock Generation 129
- Master/Slave SSI2 Interface 131
- Read Back of Residual Data 132
- CODEC Sound Interface 134
- DAI Registers 135
- DAI Control Register (DAIR) 136
- Full Bit Descriptions 137
- DAI Data Register 0 (DAIDR0) 138
- DAI Data Register 1 (DAIDR1) 139
- DAI Data Register 2 (DAIDR2) 140
- DAI Status Register (DAISR) 140
- DAI/CODEC/SSI2 141
- SSI2 Registers 144
- CODEC Register 144
- SIR Encoder 150
- UART and SIR Encoder 153
- WRDLEN Word Length 153
- Appendix A 155
- ABoot Code 155
- Boot Code 156
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