Cirrus-logic EP7309 Instrukcja Użytkownika Pobierz pdf (Strona 23)

DS507F2 Copyright Cirrus Logic, Inc. 2011

EP7309

High-Performance, Low-Power System on Chip

JTAG Interface

Parameter Symbol Min Max Units

TCK clock period

clk_per

2-ns

TCK clock high time

clk_high

1-ns

TCK clock low time

clk_low

1-ns

JTAG port setup time

JPs

-0ns

JTAG port hold time

JPh

-3ns

JTAG port clock to output

JPco

-10ns

JTAG port high impedance to valid output

JPzx

-12ns

JTAG port valid output to high impedance

JPxz

-19ns

TDO

TCK

TDI

TMS

JPh

clk_high

clk_low

JPzx

JPco

JPxz

clk_per

JPs

Figure 10. JTAG Timing Measurement

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 41 42

EP7309 Data Sheet 1
FEATURES (cont) 2
OVERVIEW (cont.) 2
Table of Contents 3
List of Figures 5
List of Tables 5
Digital Audio Interface (DAI) 7
CODEC Interface 7
Synchronous Serial Interface 8
LCD Controller 8
64-Keypad Interface 8
Interrupt Controller 8
Real-Time Clock 8
Internal Boot ROM 10
Packaging 10
Pin Multiplexing 10
System Design 11
ELECTRICAL SPECIFICATIONS 12
STANDBY 13
Timing Diagram Conventions 14
Timing Conditions 14
Static Memory 15
SSI1 Interface 20
SSI2 Interface 21
LCD Interface 22
JTAG Interface 23
Packages 24
208-Pin LQFP 25
256-Ball PBGA Ball Listing 30
CONVENTIONS 39
General Conventions 40
Pin Description Conventions 40
Ordering Information 41
Revision History 42

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