Cirrus-logic CS5550 Instrukcja Użytkownika

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comCS5550Two-channel, Low-cost A/D ConverterFeaturesz Power Consumption <

CS555010 DS630F12.1 Theory of OperationThe analog signals at the analog inputs are subjectto the gains of the input PGAs. These signals arethen sampl

CS5550DS630F1 11This linearity is guaranteed for all availablefull-scale input voltage ranges. Note that until the CS5550 is calibrated (see Cali-brat

CS555012 DS630F13.4 Calibration3.4.1 Overview of Calibration ProcessThe CS5550 offers digital calibration for offset andgain. Since both channels ha

CS5550DS630F1 13is added to the signal path to nullify the DC offsetin the system.3.4.5.2 Gain Calibration SequenceBased on the level of the positive

CS555014 DS630F1pulse-low, the duration of the INT pulse will be atleast one DCLK cycle (DCLK = MCLK / K).3.6 PCB LayoutThe CS5550 should be placed e

CS5550DS630F1 154. SERIAL PORT OVERVIEWThe CS5550's serial port incorporates a state machine with transmit/receive buffers. The state machineint

CS555016 DS630F14.1.4 Power-Up/Halt If the device is powered-down, this command will power-up the device. When powered-on, no computations will be

CS5550DS630F1 174.1.7 Register Read/Write The Read/Write command informs the state machine that a register access is required. During a read operat

CS555018 DS630F14.2 Serial Port InterfaceThe CS5550’s serial interface consists of four con-trol lines, which have the following pin-names: CS,SDI, S

CS5550DS630F1 19as well as the other defined power states of theCS5550, are described in Section 4.6).Refer to Section 5 of the data sheet to see the

CS55502 DS630F1TABLE OF CONTENTS1. PIN DESCRIPTION ...

CS555020 DS630F15. REGISTER DESCRIPTION 1. “Default**” => bit status after power-on or reset2. Any bit not labeled is Reserved. A zero should al

CS5550DS630F1 215.2 Offset RegistersAddress: 1 (Offset Register - AIN1)3 (Offset Register - AIN2) Default** = 0.000The Offset Registers are initia

CS555022 DS630F15.5 OUT1 and OUT2 Output RegistersAddress: 7 (AIN1 Output Register) 8 (AIN2 Output Register)These signed registers cont

CS5550DS630F1 23small to fit in the AIN Output Register.CRDY Conversion Ready. Indicates a new conversion is ready.OD1, OD2 Modulator oscillation dete

CS555024 DS630F16. PACKAGE DIMENSIONSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

CS5550DS630F1 3LIST OF FIGURESFigure 1. CS5550 Read and Write Timing Diagrams... 9F

CS55504 DS630F11. PIN DESCRIPTION VREFIN 12Voltage Reference InputVREFOUT 11Voltage Reference OutputAIN2- 10Differential Analog InputAIN2+ 9Different

CS5550DS630F1 52. CHARACTERISTICS/SPECIFICATIONS• Min / Max characteristics and specifications are guaranteed over all Operating Conditions.• Typical

CS55506 DS630F1ANALOG CHARACTERISTICS (Continued)Notes: 3. The minimum FSCR is limited by the maximum allowed gain register value.4. All outputs unloa

CS5550DS630F1 75 V DIGITAL CHARACTERISTICS 3 V DIGITAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max UnitHigh-Level I

CS55508 DS630F1SWITCHING CHARACTERISTICS Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency mu

CS5550DS630F1 9CSSCLKMSB MSB - 1LSBt2t1t3SDIMSB MSB - 1LSBCommand Time 8 SCLKsLSBt6MSB MSB - 1LSBMSB MSB - 1High Byte Mid Byte Low Bytett45SDI Write T