Cirrus-logic CS5484 Instrukcja Użytkownika

Copyright  Cirrus Logic, Inc. 2013(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comCS5484Four Channel Energy Measurement ICFeatures &

CS548410 DS981F3-1-0.500.510 500 1000 1500 2000 2500 3000 3500 4000 4500Percent Error (%)Current Dynamic Range (x : 1)Lagging sin(੮) = 0.5Leading sin(

CS5484DS981F3 11ANALOG CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typica

CS548412 DS981F3Notes: 5. All outputs unloaded. All inputs CMOS level.6. Temperature accuracy measured after calibration is performed.7. Measurement

CS5484DS981F3 13DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typic

CS548414 DS981F3SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typ

CS5484DS981F3 15 SDOSDIt1t2t3t4t5t6t7t8CSSCLKMSBMSB MSB-1MSB-1INTERMEDIATE BITSINTERMEDIATE BITSLSBLSBFigure 7. SPI Data and Clock TimingTXRXt9t11CSS

CS548416 DS981F3ABSOLUTE MAXIMUM RATINGSNotes: 16. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0V.17. Applies to all pins, including continuou

CS5484DS981F3 174. SIGNAL FLOW DESCRIPTION The signal flow for voltage measurement, currentmeasurement, and the other calculations is shown inFigures

CS548418 DS981F3Fine phase compensation control bits, FPCCx[8:0],provide up to 1/OWR delay in the current channel.Coarse phase compensation control bi

CS5484DS981F3 194.8.2 Line-cycle Synchronized AveragingWhen operating in Line-cycle Synchronized Averagingmode, and when line frequency measurement i

CS54842 DS981F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CS548420 DS981F34.9 Average Active Power OffsetThe average active power offset registers, P1OFF(P2OFF), can be used to offset erroneous power sources

CS5484DS981F3 215. FUNCTIONAL DESCRIPTION5.1 Power-on ResetThe CS5484 has an internal power supply supervisorcircuit that monitors the VDDA and VDDD

CS548422 DS981F35.4 Line Frequency MeasurementIf the Automatic Frequency Calculation (AFC) bit in theConfig2 register is set, the line frequency meas

CS5484DS981F3 23After reset, all four energy pulse generation blocks aredisabled (DOxMODE[3:0] = Hi-Z). To output a desiredenergy pulse to a DOx pin,

CS548424 DS981F35.5.1 Pulse RateBefore configuring the PulseRate register, the full-scalepulse rate needs to be calculated and the frequencyrange nee

CS5484DS981F3 255.7 Phase Sequence Detection Polyphase meters using multiple CS5484 devices maybe configured to sense the succession of voltagezero-c

CS548426 DS981F3The temperature sensor and V2 input share the samedelta-sigma modulator on the second voltage channel.By default, the temperature meas

CS5484DS981F3 276. HOST COMMANDS AND REGISTERS6.1 Host CommandsThe first byte sent to the CS5484 SDI/RX pin containsthe host command. Four types of h

CS548428 DS981F3Table 3. Instruction Format6.1.3 ChecksumTo improve the communication reliability on the serialinterface, the CS5484 provides a check

CS5484DS981F3 296.2 Hardware Registers Summary (Page 0)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config0 Configuration 0 Y Y 0x 40

CS5484DS981F3 35.7 Phase Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.8 Temperature Me

CS548430 DS981F353 11 0101 - Reserved -54 11 0110 - Reserved -55 11 0111 ZXNUMNum. Zero Crosses used for Line Freq. Y Y 0x00 006456 11 1000 - Reserve

CS5484DS981F3 316.3 Software Registers Summary (Page 16)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config2 Configuration 2 Y Y 0x 06

CS548432 DS981F353 11 0101 - Reserved -54* 11 0110 TGAINTemperature Gain Y Y 0x 06 B71655* 11 0111 TOFFTemperature Offset Y Y 0x D5 399856* 11 1000 -

CS5484DS981F3 336.4 Software Registers Summary (Page 17)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 V1SagDURV1 Sag Duration Y Y 0x 00

CS548434 DS981F36.5 Software Registers Summary (Page 18)Address2RA[5:0] Name Description1DSP3HOST3Default24* 01 1000 IZXLEVELZero-Cross Threshold for

CS5484DS981F3 356.6 Register Descriptions1. “Default” = bit states after power-on or reset2. DO NOT write a “1” to any unpublished register bit or to

CS548436 DS981F3NO_OSC Disable crystal oscillator (making XIN a logic-level input).0 = Crystal oscillator enabled (Default) 1 = Crystal oscillator dis

CS5484DS981F3 37DO4MODE[3:0] Output control for DO4 pin.0000 = Energy pulse generation block 1 (EPG1) output0001 = Energy pulse generation block 2 (EP

CS548438 DS981F3DO1MODE[3:0] Output control for DO1 pin.0000 = Energy pulse generation block 1 (EPG1) output0001 = Energy pulse generation block 2 (EP

CS5484DS981F3 39AFC Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is

CS54844 DS981F3LIST OF FIGURESFigure 1. Oscillator Connections...

CS548440 DS981F36.6.4 Phase Compensation (PC) – Page 0, Address 5 Default = 0x00 0000CPCC2[1:0] Coarse phase compensation control for I2 and V2.00 =

CS5484DS981F3 416.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8Default = 0x00 0001 (265.6µs at OWR = 4kHz)PulseWidth sets the energy pulse

CS548442 DS981F36.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9 Default = 0x00 0000This register controls the input to the energy pulse ge

CS5484DS981F3 436.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48 Default = 0x00 0000DONE Indicates valid count values reside i

CS548444 DS981F36.6.12 Interrupt Status (Status0) – Page 0, Address 23Default = 0x80 0000The Status0 register indicates a variety of conditions withi

CS5484DS981F3 456.6.13 Interrupt Mask (Mask) – Page 0, Address 3 Default = 0x00 0000The Mask register is used to control the activation of the INT p

CS548446 DS981F36.6.15 Chip Status 2 (Status2) – Page 0, Address 25Default = 0x00 0000This register indicates a variety of conditions within the chip

CS5484DS981F3 476.6.16 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49 Default = 0x01 999A (0.0125 or 50Hz/4.0kHz)Epsilon is the ratio

CS548448 DS981F36.6.20 Filter Settling Time for Conversion Startup (TSETTLE) – Page 16, Address 57Default = 0x00 001E (30)Sets the number of OWR samp

CS5484DS981F3 496.6.24 Voltage 1 Sag Duration (V1SagDUR) – Page 17, Address 0 Default = 0x00 0000Voltage sag duration, V1SagDUR, determines the count

CS5484DS981F3 51. OVERVIEWThe CS5484 is a CMOS power measurement integrated circuit using four  analog-to-digital convertersto measure two line volt

CS548450 DS981F36.6.28 Voltage 2 Sag Duration (V2SagDUR) – Page 17, Address 8 Default = 0x00 0000Voltage sag duration, V2SagDUR, determines the count

CS5484DS981F3 516.6.32 Voltage 1 Swell Duration (V1SwellDUR ) – Page 18, Address 46 Default = 0x00 0000Voltage swell duration, V1SwellDUR, determines

CS548452 DS981F36.6.36 Instantaneous Current 1 (I1) – Page 16, Address 2Default = 0x00 0000I1 contains instantaneous current measurements for current

CS5484DS981F3 536.6.40 RMS Current 1 (I1RMS ) – Page 16, Address 6Default = 0x00 0000I1RMS contains the root mean square (RMS) values of I1, calculat

CS548454 DS981F36.6.44 Instantaneous Active Power 2 (P2) – Page 16, Address 10Default = 0x00 0000P2 contains instantaneous power measurements for cur

CS5484DS981F3 556.6.48 Reactive Power 1 (Q1Avg ) – Page 16, Address 14Default = 0x00 0000Reactive power 1 (Q1AVG) is Q1 averaged over each low-rate i

CS548456 DS981F36.6.52 Peak Current 1 (I1PEAK) – Page 0, Address 37 Default = 0x00 0000Peak current1 (I1PEAK) contains the value of the instantaneous

CS5484DS981F3 576.6.56 Peak Current 2 (I2PEAK) – Page 0, Address 39 Default = 0x00 0000Peak current, I2PEAK, contains the value of the instantaneous

CS548458 DS981F36.6.60 Temperature (T) – Page 16, Address 27Default = 0x00 0000T contains results from the on-chip temperature measurement. By defaul

CS5484DS981F3 596.6.64 DC Offset for Current (I1DCOFF, I2DCOFF ) – Page 16, Address 32, 39Default = 0x00 0000DC offset registers I1DCOFF and I2DCOFF

CS54846 DS981F32. PIN DESCRIPTIONSDigital Pins and Serial Data I/ODigital Outputs 15,16,17,18DO1, DO2, DO3, DO4 — Configurable digital outputs for en

CS548460 DS981F36.6.68 Average Active Power Offset (P1OFF, P2OFF) – Page 16, Address 36, 43Default = 0x00 0000Average Active Power offset P1OFF (P2OF

CS5484DS981F3 616.6.72 Temperature Offset (TOFF) – Page 16, Address 55Default = 0x D5 3998Register TOFF is used to offset the Temperature register (T

CS548462 DS981F37. SYSTEM CALIBRATIONComponent tolerances, residual ADC offset, andsystem noise require a meter that needs to be calibratedbefore it m

CS5484DS981F3 637.1.1.2 AC Offset CalibrationThe AC offset calibration command measures theresidual RMS values on the current channel at zeroinput an

CS548464 DS981F33) Accumulate multiple readings of the PF1 or PF2register.4) Calculate the average power factor, PFavg.5) Calculate phase offset = arc

CS5484DS981F3 658. BASIC APPLICATION CIRCUITSFigure 25 shows the CS5484 configured to measurepower in a single-phase, 3-wire system with twovoltages a

CS548466 DS981F39. PACKAGE DIMENSIONS28 QFN (5mmX5mm BODY with EXPOSED PAD) PACKAGE DRAWINGmm inchDimension MIN NOM MAX MIN NOM MAXA 0.80 0.90 1.00 0.

CS5484DS981F3 6710. ORDERING INFORMATION11. ENVIRONMENTAL, MANUFACTURING, AND HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by

CS5484DS981F3 72.1 Analog PinsThe CS5484 has two differential inputs (VIN1VIN2)for voltage input and two differential inputsIIN1 IIN2)for cu

CS54848 DS981F32.2.4 UART/SPI™ Serial InterfaceThe CS5484 provides five pins—SSEL, RX/SDI,TX/SDO, CS, and SCLK—for communication betweena host microc

CS5484DS981F3 93. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSPOWER MEASUREMENT CHARACTERISTICSNotes: 1. Specifications guarante