Cirrus-logic AN118 Instrukcja Użytkownika Pobierz pdf (Strona 4)

AN118

4 AN118REV2

Figure 4. Write-Cycle Timing

Figure 5. Read-Cycle Timing

C

ommand Time

8SCLKs

8

SCLKs Clear SDO Flag

Data SDO Continuous Conversion Read

S

DO

SCLK

SDI

t

*

d

D

ata Time

24 SCLKs

M

SB

L

SB

*

td = XIN/OWR clock cycles for each conversion except the

first conversion which will take XIN/OWR + 7 clock cycles

X

IN/OWR

Clock Cycles

Figure 6. Conversion/Acquisition Cycle Timing

1 2 3 4 5 6 7 8 9 ... 31 32

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