Cirrus-logic CS61884 Instrukcja Użytkownika Strona 72
- Strona / 72
- Spis treści
- BOOKMARKI
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1. PINOUT - LQFP 7
- 2. PINOUT - LFBGA 8
- 3. PIN DESCRIPTIONS 9
- 3.1 Power Supplies 9
- 3.2 Control 10
- 3.3 Address Inputs/Loopbacks 14
- 3.4 Cable Select 15
- 3.6 Digital Rx/Tx Data I/O 16
- 3.7 Analog RX/TX Data I/O 19
- 3.9 Miscellaneous 21
- 3.8 JTAG Test Interface 21
- 4. OPERATION 22
- 5. POWER-UP 22
- 6. MASTER CLOCK 22
- 7. G.772 MONITORING 22
- DS485F3 23 23
- 9. TRANSMITTER 24
- 9.1 Bipolar Mode 25
- 9.2 Unipolar Mode 25
- 9.3 RZ Mode 25
- 9.5 Transmit All Ones (TAOS) 25
- 26 DS485F3 26
- 10.3 RZ Output Mode 27
- 10.5 Loss-of-Signal (LOS) 27
- 11. JITTER ATTENUATOR 28
- 12. OPERATIONAL SUMMARY 29
- 12.1 Loopbacks 29
- 12.2 Analog Loopback 29
- 12.3 Digital Loopback 30
- 12.4 Remote Loopback 30
- DS485F3 31 31
- 13. HOST MODE 32
- 13.1 SOFTWARE RESET 32
- 13.2 Serial Port Operation 32
- 13.3 Parallel Port Operation 33
- 13.4 Register Set 34
- TAOS Enable Register (03h) 35
- DFM Status Register (05h) 35
- (Continued) 37
- 14.33 Status Registers 42
- 15. ARBITRARY WAVEFORM 43
- GENERATOR 43
- 44 DS485F3 44
- 16. JTAG SUPPORT 45
- 16.1 TAP Controller 45
- 16.1.1 JTAG Reset 45
- 16.1.2 Test-Logic-Reset 45
- 16.1.3 Run-Test-Idle 45
- 46 DS485F3 46
- 18. APPLICATIONS 51
- 18.4 Line Protection 53
- 19.3 Digital Characteristics 55
- 58 DS485F3 58
- RPOS/RNEG 60
- CLKE = 1 60
- CLKE = 0 60
- DS485F3 63 63
- 64 DS485F3 64
- 66 DS485F3 66
- DS485F3 67 67
- DS485F3 69 69
- 21. LFBGA PACKAGE DIMENSIONS 70
- 144L LQFP PACKAGE DRAWING 71
- 23. ORDERING INFORMATION 72
- 25. REVISION HISTORY 72
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