Cirrus-logic CS5509 Instrukcja Użytkownika

1Copyright  Cirrus Logic, Inc. 2009(All Rights Reserved)http://www.cirrus.comCS5509Single-supply, 16-bit A/D ConverterFeatures Delta-sigma A/D Conve

CS550910 DS125F3GENERAL DESCRIPTIONThe CS5509 is a low power, 16-bit, monolithicCMOS A/D converter designed specifically formeasurement of dc signals.

CS5509DS125F3 11put signals. The converter can be used to convertboth unipolar and bipolar signals by changing theBP/UP pin. Recalibration is not requ

CS550912 DS125F3in the reference without recalibration, accommo-dating ratiometric applications.Analog Input RangeThe analog input range is set by the

CS5509DS125F3 13An equation for the maximum acceptable sourceresistance is derived.This equation assumes that the offset voltage of thebuffer is 100 m

CS550914 DS125F3line frequency interference will occur with theCS5509 running at 32.768kHz.Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)Anti-Al

CS5509DS125F3 15to prevent aliasing. Spectral components greaterthan one half the output word rate on the VREF in-puts (VREF+ and VREF-) may also be a

CS550916 DS125F3Power Supplies and Grounding The analog and digital supply pins to the CS5509are brought out on separate pins to minimize noisecouplin

CS5509DS125F3 17Figure 9a. System Connection Diagram Using a Single SupplyCS5509+5VAnalogSupplyVD+VA+VREF+VREF-GND0.1 µF 0.1 µF87910111213+-AnalogSig

CS550918 DS125F3Figure 9b. System Connection Diagram Using Split SuppliesCS5509+5VAnalogSupplyVD+VA+VREF+VREF-GND0.1 µF 0.1 µF87910111213+-AnalogSign

CS5509DS125F3 19PIN DESCRIPTIONS** Pinout applies to both PDIP and SOICClock GeneratorXIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.A gate inside the

CS55092 DS125F3Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509's sourceimpedance requirements. Refe

CS550920 DS125F3Control Input PinsCAL - Calibrate, Pin 3.When taken high the same time that the CONV pin is taken high the converter will perform asel

CS5509DS125F3 21SPECIFICATION DEFINITIONSLinearity ErrorThe deviation of a code from a straight line which connects the two endpoints of the A/DConver

CS550922 DS125F3PACKAGE DIMENSIONSSOICMILLIMETERSINCHESMIN MAXMAXMIN0.0950.1052.412.670.0080.0150.2030.3810.3980.42010.1110.670.0200.0130.510.330.0160

CS5509DS125F3 23ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.Model

CS550924 DS125F3REVISION HISTORY Revision Date ChangesF1 Aug ‘97 First “final” release.F2 Aug ‘05 Added lead-free device ordering info. Added legal no

CS5509DS125F3 3Notes: 8. All measurements are performed under static conditions.9. Iout = -100 µA. This guarantees the ability to drive one TTL load.

CS55094 DS125F3Notes: 10. Specified using 10% and 90% points on waveform of interest.11. An internal power-on-reset is activated whenever power is app

CS5509DS125F3 53.3V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Not

CS55096 DS125F3tccwXINCalibration StandbyStandbytscltcalXIN/2STATECALCONVFigure 1. Calibration Timing (Not to Scale)XINXIN/2tbuhConversion StandbySta

CS5509DS125F3 7Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The

CS55098 DS125F3SCLK(i)MSB-1MSB MSB-2SDATA(o) Hi-ZMSB-1MSB LSB+2 LSB+1 LSBSCLK(i)SDATA(o) Hi-Ztfd1tcsdtddtphtpltddtcsdCSCSDRDYDRDYtfd2Figure 3. Timing

CS5509DS125F3 9Notes: 19. All voltages with respect to ground.20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a cor