Cirrus-logic CDB61884 Instrukcja Użytkownika

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CDB6188410 DS485DB1following registers do not have the automatic readback function:–AWGPhaseAddress– AWG Phase Data,– Software Reset registers.4.1 Sta

CDB61884DS485DB1 114.3.1 Clear All Button DescriptionThe CLR All Button shown Figure 14 is used to setall the bits in the corresponding register to 0s

CDB6188412 DS485DB15. CS61884 CONFIGURATION SCREENS5.1 Choose Parallel Port SettingsThe opening screen shown before in Figure 11 andnow in Figure 19 i

CDB61884DS485DB1 135.3 Loopback /Bits Clock ScreenThe Loopback /Bits Clock Register tabbed screen shown in Figure 20 allows access to the following re

CDB6188414 DS485DB15.4 LOS/AIS/DFM/JA Register ScreenThe LOS/AIS/DFM/JA Register tabbed screen shown in Figure 21 allows access to the following regis

CDB61884DS485DB1 155.5 Transmitter Register ScreenThe Transmitter Register screen shown in Figure 22 consists of the following registers:– Automatic T

CDB6188416 DS485DB15.6 AWG Register ScreenThe AWG Register screen shown in Figure 23 allows access to the following AWG registers:– AWG Broadcast– AWG

CDB61884DS485DB1 175.7 Global Control Register ScreenFigure 24 shows the Global Control Register (GCR) register screen, The GCR register screen consis

CDB6188418 DS485DB16. BOARD CONFIGURATIONS6.1 E1 75 Ω Mode SetupTable 4 shows the position of the different switches and jumpers used to set up the CD

CDB61884DS485DB1 196.2 E1 120 Ω Mode SetupTable 5 shows the position of the different switches and jumpers used to set up the CDB61884 evaluationboard

CDB618842 DS485DB1TABLE OF CONTENTS1. CDB61884 EVALUATION BOARD LAYOUT ... 42.

CDB6188420 DS485DB16.3 T1/J1 100 Ω Mode SetupTable 6 shows the position of the different switches and jumpers used to set up the CDB61884 evaluationbo

CDB61884DS485DB1 217. EVALUATION HINTS– Pin #1 of the socket is indicated by an arrow with U1 below it.– A short in the desired position must be place

CDB61884DS485DB1 35. CS61884 CONFIGURATION SCREENS ... 125.1 Choose Parall

CDB618844 DS485DB11. CDB61884 EVALUATION BOARD LAYOUTFigure 1. CDB61884 Board Layout

CDB61884DS485DB1 52. BOARD COMPONENT DESCRIPTIONS2.1 Power ConnectionsPower for the evaluation board is supplied by anexternal +3.3 V DC power supply.

CDB618846 DS485DB12.3 Operating Mode SelectionThe operating mode for the CS61884 can be select-ed by setting switch S15 to one of the positionsshown i

CDB61884DS485DB1 7mitters in a high impedance state. Removing theshorting block, enables the transmitters. SeeFigure 5.2.6 Clock Edge SelectionIn cloc

CDB618848 DS485DB1In host mode, switches S12 through S14 (LEN2-0)must be set to the open (middle) position to allowhost processor control.2.10 Line Im

CDB61884DS485DB1 9in the open “HIGH” position selects multiplex andthe closed “LOW” position selects Non-multiplex2.14 Digital Signal ConnectionsThere